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32 #ifndef __ARCH_SPARC_INTERRUPT_HH__
33 #define __ARCH_SPARC_INTERRUPT_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "cpu/thread_context.hh"
38 #include "params/SparcInterrupts.hh"
39 #include "sim/sim_object.hh"
44 class Interrupts : public SimObject
49 uint64_t interrupts[NumInterruptTypes];
55 setCPU(BaseCPU * _cpu)
60 typedef SparcInterruptsParams Params;
65 return dynamic_cast<const Params *>(_params);
68 Interrupts(Params * p) : SimObject(p), cpu(NULL)
74 InterruptLevel(uint64_t softint)
76 if (softint & 0x10000 || softint & 0x1)
80 while (level > 0 && !(1 << level & softint))
82 if (1 << level & softint)
88 post(int int_num, int index)
90 DPRINTF(Interrupt, "Interrupt %d:%d posted\n", int_num, index);
91 assert(int_num >= 0 && int_num < NumInterruptTypes);
92 assert(index >= 0 && index < 64);
94 interrupts[int_num] |= ULL(1) << index;
95 intStatus |= ULL(1) << int_num;
99 clear(int int_num, int index)
101 DPRINTF(Interrupt, "Interrupt %d:%d cleared\n", int_num, index);
102 assert(int_num >= 0 && int_num < NumInterruptTypes);
103 assert(index >= 0 && index < 64);
105 interrupts[int_num] &= ~(ULL(1) << index);
106 if (!interrupts[int_num])
107 intStatus &= ~(ULL(1) << int_num);
113 for (int i = 0; i < NumInterruptTypes; ++i) {
120 checkInterrupts(ThreadContext *tc) const
126 getInterrupt(ThreadContext *tc)
128 int hpstate = tc->readMiscRegNoEffect(MISCREG_HPSTATE);
129 int pstate = tc->readMiscRegNoEffect(MISCREG_PSTATE);
130 bool ie = pstate & PSTATE::ie;
132 // THESE ARE IN ORDER OF PRIORITY
133 // since there are early returns, and the highest
134 // priority interrupts should get serviced,
135 // it is v. important that new interrupts are inserted
136 // in the right order of processing
137 if (hpstate & HPSTATE::hpriv) {
139 if (interrupts[IT_HINTP]) {
140 // This will be cleaned by a HINTP write
141 return new HstickMatch;
143 if (interrupts[IT_INT_VEC]) {
144 // this will be cleared by an ASI read (or write)
145 return new InterruptVector;
149 if (interrupts[IT_TRAP_LEVEL_ZERO]) {
150 // this is cleared by deasserting HPSTATE::tlz
151 return new TrapLevelZero;
153 // HStick matches always happen in priv mode (ie doesn't matter)
154 if (interrupts[IT_HINTP]) {
155 return new HstickMatch;
157 if (interrupts[IT_INT_VEC]) {
158 // this will be cleared by an ASI read (or write)
159 return new InterruptVector;
162 if (interrupts[IT_CPU_MONDO]) {
165 if (interrupts[IT_DEV_MONDO]) {
168 if (interrupts[IT_SOFT_INT]) {
169 int level = InterruptLevel(interrupts[IT_SOFT_INT]);
170 return new InterruptLevelN(level);
173 if (interrupts[IT_RES_ERROR]) {
174 return new ResumableError;
182 updateIntrInfo(ThreadContext *tc)
190 assert(int_num >= 0 && int_num < NumInterruptTypes);
191 return interrupts[int_num];
195 serialize(std::ostream &os)
197 SERIALIZE_ARRAY(interrupts,NumInterruptTypes);
198 SERIALIZE_SCALAR(intStatus);
202 unserialize(Checkpoint *cp, const std::string §ion)
204 UNSERIALIZE_ARRAY(interrupts,NumInterruptTypes);
205 UNSERIALIZE_SCALAR(intStatus);
208 } // namespace SPARC_ISA
210 #endif // __ARCH_SPARC_INTERRUPT_HH__