CPU: Create a microcode ROM object in the CPU which is defined by the ISA.
[gem5.git] / src / arch / sparc / intregfile.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32 #ifndef __ARCH_SPARC_INTREGFILE_HH__
33 #define __ARCH_SPARC_INTREGFILE_HH__
34
35 #include "arch/sparc/isa_traits.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/bitfield.hh"
38
39 #include <string>
40
41 class Checkpoint;
42
43 namespace SparcISA
44 {
45 class RegFile;
46
47 //This function translates integer register file indices into names
48 std::string getIntRegName(RegIndex);
49
50 const int NumIntArchRegs = 32;
51 const int NumIntRegs = (MaxGL + 1) * 8 + NWindows * 16 + NumMicroIntRegs;
52
53 class IntRegFile
54 {
55 private:
56 friend class RegFile;
57 protected:
58 //The number of bits needed to index into each 8 register frame
59 static const int FrameOffsetBits = 3;
60 //The number of bits to choose between the 4 sets of 8 registers
61 static const int FrameNumBits = 2;
62
63 //The number of registers per "frame" (8)
64 static const int RegsPerFrame = 1 << FrameOffsetBits;
65 //A mask to get the frame number
66 static const uint64_t FrameNumMask =
67 (FrameNumBits == sizeof(int)) ?
68 (unsigned int)(-1) :
69 (1 << FrameNumBits) - 1;
70 static const uint64_t FrameOffsetMask =
71 (FrameOffsetBits == sizeof(int)) ?
72 (unsigned int)(-1) :
73 (1 << FrameOffsetBits) - 1;
74
75 IntReg regGlobals[MaxGL+1][RegsPerFrame];
76 IntReg regSegments[2 * NWindows][RegsPerFrame];
77 IntReg microRegs[NumMicroIntRegs];
78 IntReg regs[NumIntRegs];
79
80 enum regFrame {Globals, Outputs, Locals, Inputs, NumFrames};
81
82 IntReg * regView[NumFrames];
83
84 static const int RegGlobalOffset = 0;
85 static const int FrameOffset = (MaxGL + 1) * RegsPerFrame;
86 int offset[NumFrames];
87
88 public:
89
90 int flattenIndex(int reg);
91
92 void clear();
93
94 IntRegFile();
95
96 IntReg readReg(int intReg);
97
98 void setReg(int intReg, const IntReg &val);
99
100 void serialize(std::ostream &os);
101
102 void unserialize(Checkpoint *cp, const std::string &section);
103
104 protected:
105 //This doesn't effect the actual CWP register.
106 //It's purpose is to adjust the view of the register file
107 //to what it would be if CWP = cwp.
108 void setCWP(int cwp);
109
110 void setGlobals(int gl);
111 };
112 }
113
114 #endif