src/arch/sparc/isa/bitfields.isa

   1 // Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 // All rights reserved.
   3 //
   4 // Redistribution and use in source and binary forms, with or without
   5 // modification, are permitted provided that the following conditions are
   6 // met: redistributions of source code must retain the above copyright
   7 // notice, this list of conditions and the following disclaimer;
   8 // redistributions in binary form must reproduce the above copyright
   9 // notice, this list of conditions and the following disclaimer in the
  10 // documentation and/or other materials provided with the distribution;
  11 // neither the name of the copyright holders nor the names of its
  12 // contributors may be used to endorse or promote products derived from
  13 // this software without specific prior written permission.
  14 //
  15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 //
  27 // Authors: Ali Saidi
  28 //          Gabe Black
  29 //          Steve Reinhardt
  30
  31 ////////////////////////////////////////////////////////////////////
  32 //
  33 // Bitfield definitions.
  34 //
  35
  36 // Bitfields are shared liberally between instruction formats, so they are
  37 // simply defined alphabetically
  38
  39 def bitfield A          <29>;
  40 def bitfield BPCC       <21:20>; // for BPcc & FBPcc
  41 def bitfield FCMPCC     <26:25>; // for FCMP & FCMPEa
  42 def bitfield FMOVCC     <13:11>; // for FMOVcc
  43 def bitfield CC         <12:11>; // for MOVcc & Tcc
  44 def bitfield MOVCC3     <18>; // also for MOVcc
  45 def bitfield CMASK      <6:4>;
  46 def bitfield COND2      <28:25>;
  47 def bitfield COND4      <17:14>;
  48 def bitfield D16HI      <21:20>;
  49 def bitfield D16LO      <13:0>;
  50 def bitfield DISP19     <18:0>;
  51 def bitfield DISP22     <21:0>;
  52 def bitfield DISP30     <29:0>;
  53 def bitfield FCN        <29:25>;
  54 def bitfield I          <13>;
  55 def bitfield IMM_ASI    <12:5>;
  56 def bitfield IMM22      <21:0>;
  57 def bitfield M5FUNC     <15:7>;
  58 def bitfield MMASK      <3:0>;
  59 def bitfield OP         <31:30>;
  60 def bitfield OP2        <24:22>;
  61 def bitfield OP3        <24:19>;
  62 def bitfield OPF        <13:5>;
  63 def bitfield OPF_CC     <13:11>;
  64 def bitfield OPF_LOW5   <9:5>;
  65 def bitfield OPF_LOW6   <10:5>;
  66 def bitfield P          <19>;
  67 def bitfield RCOND2     <27:25>;
  68 def bitfield RCOND3     <12:10>;
  69 def bitfield RCOND4     <12:10>;
  70 def bitfield RD         <29:25>;
  71 def bitfield RS1        <18:14>;
  72 def bitfield RS2        <4:0>;
  73 def bitfield SHCNT32    <4:0>;
  74 def bitfield SHCNT64    <5:0>;
  75 def bitfield SIMM10     <9:0>;
  76 def bitfield SIMM11     <10:0>;
  77 def bitfield SIMM13     <12:0>;
  78 def bitfield SW_TRAP    <7:0>;
  79 def bitfield X          <12>;
  80
  81 // Extended bitfields which aren't part of the actual instruction.
  82
  83 def bitfield EXT_ASI    <39:32>;