1 // Copyright (c) 2006-2007 The Regents of The University of Michigan
2 // All rights reserved.
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5 // modification, are permitted provided that the following conditions are
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31 ////////////////////////////////////////////////////////////////////
33 // The actual decoder specification
36 decode OP default Unknown::unknown()
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
48 0x8: bpa(19, annul_code={{
49 NPC = xc->readPC() + disp;
60 0x0: bpcci(19, test={{passesCondition(Ccr<3:0>, COND2)}});
61 0x2: bpccx(19, test={{passesCondition(Ccr<7:4>, COND2)}});
68 0x8: ba(22, annul_code={{
69 NPC = xc->readPC() + disp;
78 default: bicc(22, test={{passesCondition(Ccr<3:0>, COND2)}});
85 0x1: bpreq(test={{Rs1.sdw == 0}});
86 0x2: bprle(test={{Rs1.sdw <= 0}});
87 0x3: bprl(test={{Rs1.sdw < 0}});
88 0x5: bprne(test={{Rs1.sdw != 0}});
89 0x6: bprg(test={{Rs1.sdw > 0}});
90 0x7: bprge(test={{Rs1.sdw >= 0}});
93 //SETHI (or NOP if rd == 0 and imm == 0)
94 0x4: SetHi::sethi({{Rd.udw = imm;}});
99 0x8: fbpa(22, annul_code={{
100 NPC = xc->readPC() + disp;
109 default: decode BPCC {
110 0x0: fbpfcc0(19, test=
111 {{passesFpCondition(Fsr<11:10>, COND2)}});
112 0x1: fbpfcc1(19, test=
113 {{passesFpCondition(Fsr<33:32>, COND2)}});
114 0x2: fbpfcc2(19, test=
115 {{passesFpCondition(Fsr<35:34>, COND2)}});
116 0x3: fbpfcc3(19, test=
117 {{passesFpCondition(Fsr<37:36>, COND2)}});
125 0x8: fba(22, annul_code={{
126 NPC = xc->readPC() + disp;
135 default: fbfcc(22, test=
136 {{passesFpCondition(Fsr<11:10>, COND2)}});
140 0x1: BranchN::call(30, {{
142 R15 = (xc->readPC())<31:0>;
149 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
150 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
151 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
152 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
153 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
154 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
155 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
156 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
157 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
158 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
160 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
164 Rd.sdw = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
167 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
169 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
170 else Rd.udw = Rs1.udw / Rs2_or_imm13;
173 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
176 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
177 if(Rd.udw >> 32 != 0)
182 if(Rs2_or_imm13.sdw == 0)
183 fault = new DivisionByZero;
186 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
187 if((int64_t)Rd.udw >= std::numeric_limits<int32_t>::max())
189 else if((int64_t)Rd.udw <= std::numeric_limits<int32_t>::min())
190 Rd.udw = ULL(0xFFFFFFFF80000000);
196 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
197 Rd = res = op1 + op2;
199 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
200 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
201 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
203 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
204 Rd = res = op1 - op2;
206 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
207 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
208 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
210 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
211 Rd = res = op1 + op2 + Ccr<0:>;
213 0x1A: IntOpCcRes::umulcc({{
215 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
216 Y = resTemp<63:32>;}});
217 0x1B: IntOpCcRes::smulcc({{
219 Rd = resTemp = sext<32>(Rs1.sdw<31:0>) * sext<32>(Rs2_or_imm13<31:0>);
220 Y = resTemp<63:32>;}});
222 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
223 Rd = res = op1 - op2 - Ccr<0:>;
225 0x1D: IntOpCcRes::udivxcc({{
226 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
227 else Rd = Rs1.udw / Rs2_or_imm13.udw;}});
228 0x1E: IntOpCcRes::udivcc({{
230 uint32_t val2 = Rs2_or_imm13.udw;
231 int32_t overflow = 0;
232 if(val2 == 0) fault = new DivisionByZero;
235 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
236 overflow = (resTemp<63:32> != 0);
237 if(overflow) Rd = resTemp = 0xFFFFFFFF;
240 }}, iv={{overflow}});
241 0x1F: IntOpCcRes::sdivcc({{
242 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
243 bool overflow = false, underflow = false;
244 if(val2 == 0) fault = new DivisionByZero;
247 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
248 overflow = ((int64_t)Rd >= std::numeric_limits<int32_t>::max());
249 underflow = ((int64_t)Rd <= std::numeric_limits<int32_t>::min());
250 if(overflow) Rd = 0x7FFFFFFF;
251 else if(underflow) Rd = ULL(0xFFFFFFFF80000000);
253 }}, iv={{overflow || underflow}});
255 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
256 Rd = res = Rs1 + op2;
258 (op1 & mask(2)) || (op2 & mask(2)) ||
259 findOverflow(32, res, op1, op2)
262 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
263 Rd = res = Rs1 - op2;
265 (op1 & mask(2)) || (op2 & mask(2)) ||
266 findOverflow(32, res, op1, ~op2)
269 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
270 Rd = res = op1 + op2;
271 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
272 findOverflow(32, res, op1, op2);
273 if(overflow) fault = new TagOverflow;
274 }}, iv={{overflow}});
276 int64_t res, op1 = Rs1, op2 = Rs2_or_imm13;
277 Rd = res = op1 - op2;
278 bool overflow = (op1 & mask(2)) || (op2 & mask(2)) ||
279 findOverflow(32, res, op1, ~op2);
280 if(overflow) fault = new TagOverflow;
281 }}, iv={{overflow}}, sub=True);
283 int32_t savedLSB = Rs1<0:>;
286 int64_t multiplicand = Rs2_or_imm13;
288 int32_t partialP = Rs1<31:1> |
289 ((Ccr<3:3> ^ Ccr<1:1>) << 31);
291 int32_t added = Y<0:> ? multiplicand : 0;
292 int64_t res, op1 = partialP, op2 = added;
293 Rd = res = partialP + added;
295 Y = Y<31:1> | (savedLSB << 31);
301 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
302 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
305 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
306 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
309 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
310 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
313 0x00: NoPriv::rdy({{Rd = Y<31:0>;}});
314 //1 should cause an illegal instruction exception
315 0x02: NoPriv::rdccr({{Rd = Ccr;}});
316 0x03: NoPriv::rdasi({{Rd = Asi;}});
317 0x04: Priv::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
318 0x05: NoPriv::rdpc({{
320 Rd = (xc->readPC())<31:0>;
322 Rd = xc->readPC();}});
323 0x06: NoPriv::rdfprs({{
324 //Wait for all fpops to finish.
327 //7-14 should cause an illegal instruction exception
329 0x0: Nop::stbar({{/*stuff*/}}, IsWriteBarrier, MemWriteOp);
330 0x1: Nop::membar({{/*stuff*/}}, IsMemBarrier, MemReadOp);
332 0x10: Priv::rdpcr({{Rd = Pcr;}});
333 0x11: Priv::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
334 //0x12 should cause an illegal instruction exception
335 0x13: NoPriv::rdgsr({{
336 fault = checkFpEnableFault(xc);
341 //0x14-0x15 should cause an illegal instruction exception
342 0x16: Priv::rdsoftint({{Rd = Softint;}});
343 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
344 0x18: Priv::rdstick({{Rd = Stick}}, {{Stick<63:>}});
345 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
346 0x1A: Priv::rdstrand_sts_reg({{
347 if(Pstate<2:> && !Hpstate<2:>)
348 Rd = StrandStsReg<0:>;
352 //0x1A is supposed to be reserved, but it reads the strand
354 //0x1B-0x1F should cause an illegal instruction exception
357 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
358 0x01: HPriv::rdhprhtstate({{Rd = Htstate;}}, checkTl=true);
359 //0x02 should cause an illegal instruction exception
360 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
361 //0x04 should cause an illegal instruction exception
362 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
363 0x06: HPriv::rdhprhver({{Rd = Hver;}});
364 //0x07-0x1E should cause an illegal instruction exception
365 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
368 0x00: Priv::rdprtpc({{Rd = Tpc;}}, checkTl=true);
369 0x01: Priv::rdprtnpc({{Rd = Tnpc;}}, checkTl=true);
370 0x02: Priv::rdprtstate({{Rd = Tstate;}}, checkTl=true);
371 0x03: Priv::rdprtt({{Rd = Tt;}}, checkTl=true);
372 0x04: Priv::rdprtick({{Rd = Tick;}});
373 0x05: Priv::rdprtba({{Rd = Tba;}});
374 0x06: Priv::rdprpstate({{Rd = Pstate;}});
375 0x07: Priv::rdprtl({{Rd = Tl;}});
376 0x08: Priv::rdprpil({{Rd = Pil;}});
377 0x09: Priv::rdprcwp({{Rd = Cwp;}});
378 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
379 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
380 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
381 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
382 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
383 //0x0F should cause an illegal instruction exception
384 0x10: Priv::rdprgl({{Rd = Gl;}});
385 //0x11-0x1F should cause an illegal instruction exception
387 0x2B: BasicOperate::flushw({{
388 if(NWindows - 2 - Cansave != 0)
391 fault = new SpillNOther(4*Wstate<5:3>);
393 fault = new SpillNNormal(4*Wstate<2:0>);
401 if(passesCondition(Fsr<11:10>, COND4))
407 if(passesCondition(Fsr<33:32>, COND4))
413 if(passesCondition(Fsr<35:34>, COND4))
419 if(passesCondition(Fsr<37:36>, COND4))
428 if(passesCondition(Ccr<3:0>, COND4))
434 if(passesCondition(Ccr<7:4>, COND4))
442 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
443 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
445 0x2E: Trap::popc({{fault = new IllegalInstruction;}});
448 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
449 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
450 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
451 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
452 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
453 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
456 0x00: NoPriv::wry({{Y = (Rs1 ^ Rs2_or_imm13)<31:0>;}});
457 //0x01 should cause an illegal instruction exception
458 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
459 0x03: NoPriv::wrasi({{Asi = Rs1 ^ Rs2_or_imm13;}});
460 //0x04-0x05 should cause an illegal instruction exception
461 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
462 //0x07-0x0E should cause an illegal instruction exception
463 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
464 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
465 0x11: Priv::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
466 //0x12 should cause an illegal instruction exception
467 0x13: NoPriv::wrgsr({{
468 if(Fprs<2:> == 0 || Pstate<4:> == 0)
469 return new FpDisabled;
470 Gsr = Rs1 ^ Rs2_or_imm13;
472 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
473 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
474 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
475 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
476 0x18: NoPriv::wrstick({{
478 return new IllegalInstruction;
479 Stick = Rs1 ^ Rs2_or_imm13;
481 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
482 0x1A: Priv::wrstrand_sts_reg({{
483 StrandStsReg = Rs1 ^ Rs2_or_imm13;
485 //0x1A is supposed to be reserved, but it writes the strand
487 //0x1B-0x1F should cause an illegal instruction exception
491 assert(Cansave < NWindows - 2);
492 assert(Otherwin || Canrestore);
493 Cansave = Cansave + 1;
495 Canrestore = Canrestore - 1;
497 Otherwin = Otherwin - 1;
499 0x1: Priv::restored({{
500 assert(Cansave || Otherwin);
501 assert(Canrestore < NWindows - 2);
502 Canrestore = Canrestore + 1;
504 Cansave = Cansave - 1;
506 Otherwin = Otherwin - 1;
508 if(Cleanwin < NWindows - 1)
509 Cleanwin = Cleanwin + 1;
514 {{Tpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
515 0x01: Priv::wrprtnpc(
516 {{Tnpc = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
517 0x02: Priv::wrprtstate(
518 {{Tstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
520 {{Tt = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
521 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
522 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
523 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
524 0x07: Priv::wrprtl({{
525 if(Pstate<2:> && !Hpstate<2:>)
526 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
528 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
530 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
531 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
532 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
533 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
534 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
535 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
536 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
537 //0x0F should cause an illegal instruction exception
538 0x10: Priv::wrprgl({{
539 if(Pstate<2:> && !Hpstate<2:>)
540 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
542 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
544 //0x11-0x1F should cause an illegal instruction exception
547 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
548 0x01: HPriv::wrhprhtstate(
549 {{Htstate = Rs1 ^ Rs2_or_imm13;}}, checkTl=true);
550 //0x02 should cause an illegal instruction exception
551 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
552 //0x04 should cause an illegal instruction exception
553 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
554 //0x06-0x01D should cause an illegal instruction exception
555 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
559 0x01: fmovs({{Frds.uw = Frs2s.uw;}});
560 0x02: fmovd({{Frd.udw = Frs2.udw;}});
561 0x03: FpUnimpl::fmovq();
562 0x05: fnegs({{Frds.uw = Frs2s.uw ^ (1UL << 31);}});
563 0x06: fnegd({{Frd.udw = Frs2.udw ^ (1ULL << 63);}});
564 0x07: FpUnimpl::fnegq();
565 0x09: fabss({{Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;}});
566 0x0A: fabsd({{Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;}});
567 0x0B: FpUnimpl::fabsq();
568 0x29: fsqrts({{Frds.sf = std::sqrt(Frs2s.sf);}});
569 0x2A: fsqrtd({{Frd.df = std::sqrt(Frs2.df);}});
570 0x2B: FpUnimpl::fsqrtq();
571 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
572 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
573 0x43: FpUnimpl::faddq();
574 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
575 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df; }});
576 0x47: FpUnimpl::fsubq();
577 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
578 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
579 0x4B: FpUnimpl::fmulq();
580 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
581 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
582 0x4F: FpUnimpl::fdivq();
583 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
584 0x6E: FpUnimpl::fdmulq();
585 0x81: fstox({{Frd.sdw = static_cast<int64_t>(Frs2s.sf);}});
586 0x82: fdtox({{Frd.sdw = static_cast<int64_t>(Frs2.df);}});
587 0x83: FpUnimpl::fqtox();
588 0x84: fxtos({{Frds.sf = static_cast<float>(Frs2.sdw);}});
589 0x88: fxtod({{Frd.df = static_cast<double>(Frs2.sdw);}});
590 0x8C: FpUnimpl::fxtoq();
591 0xC4: fitos({{Frds.sf = static_cast<float>(Frs2s.sw);}});
592 0xC6: fdtos({{Frds.sf = Frs2.df;}});
593 0xC7: FpUnimpl::fqtos();
594 0xC8: fitod({{Frd.df = static_cast<double>(Frs2s.sw);}});
595 0xC9: fstod({{Frd.df = Frs2s.sf;}});
596 0xCB: FpUnimpl::fqtod();
597 0xCC: FpUnimpl::fitoq();
598 0xCD: FpUnimpl::fstoq();
599 0xCE: FpUnimpl::fdtoq();
601 Frds.sw = static_cast<int32_t>(Frs2s.sf);
604 Fsr = insertBits(Fsr, 4,0, 0x01);
607 Frds.sw = static_cast<int32_t>(Frs2.df);
610 Fsr = insertBits(Fsr, 4,0, 0x01);
612 0xD3: FpUnimpl::fqtoi();
613 default: FailUnimpl::fpop1();
619 if(passesFpCondition(Fsr<11:10>, COND4))
625 if(passesFpCondition(Fsr<11:10>, COND4))
630 0x03: FpUnimpl::fmovq_fcc0();
643 0x27: FpUnimpl::fmovrqz();
645 if(passesFpCondition(Fsr<33:32>, COND4))
651 if(passesFpCondition(Fsr<33:32>, COND4))
656 0x43: FpUnimpl::fmovq_fcc1();
669 0x47: FpUnimpl::fmovrqlez();
672 if(isnan(Frs1s) || isnan(Frs2s))
674 else if(Frs1s < Frs2s)
676 else if(Frs1s > Frs2s)
680 uint8_t firstbit = 10;
682 firstbit = FCMPCC * 2 + 30;
683 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
687 if(isnan(Frs1) || isnan(Frs2))
695 uint8_t firstbit = 10;
697 firstbit = FCMPCC * 2 + 30;
698 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
700 0x53: FpUnimpl::fcmpq();
703 if(isnan(Frs1s) || isnan(Frs2s))
704 fault = new FpExceptionIEEE754;
707 else if(Frs1s > Frs2s)
709 uint8_t firstbit = 10;
711 firstbit = FCMPCC * 2 + 30;
712 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
716 if(isnan(Frs1) || isnan(Frs2))
717 fault = new FpExceptionIEEE754;
722 uint8_t firstbit = 10;
724 firstbit = FCMPCC * 2 + 30;
725 Fsr = insertBits(Fsr, firstbit +1, firstbit, fcc);
727 0x57: FpUnimpl::fcmpeq();
740 0x67: FpUnimpl::fmovrqlz();
742 if(passesFpCondition(Fsr<35:34>, COND4))
748 if(passesFpCondition(Fsr<35:34>, COND4))
753 0x83: FpUnimpl::fmovq_fcc2();
766 0xA7: FpUnimpl::fmovrqnz();
768 if(passesFpCondition(Fsr<37:36>, COND4))
774 if(passesFpCondition(Fsr<37:36>, COND4))
779 0xC3: FpUnimpl::fmovq_fcc3();
792 0xC7: FpUnimpl::fmovrqgz();
805 0xE7: FpUnimpl::fmovrqgez();
807 if(passesCondition(Ccr<3:0>, COND4))
813 if(passesCondition(Ccr<3:0>, COND4))
818 0x103: FpUnimpl::fmovq_icc();
820 if(passesCondition(Ccr<7:4>, COND4))
826 if(passesCondition(Ccr<7:4>, COND4))
831 0x183: FpUnimpl::fmovq_xcc();
832 default: FailUnimpl::fpop2();
835 //This used to be just impdep1, but now it's a whole bunch
838 0x00: FailUnimpl::edge8();
839 0x01: FailUnimpl::edge8n();
840 0x02: FailUnimpl::edge8l();
841 0x03: FailUnimpl::edge8ln();
842 0x04: FailUnimpl::edge16();
843 0x05: FailUnimpl::edge16n();
844 0x06: FailUnimpl::edge16l();
845 0x07: FailUnimpl::edge16ln();
846 0x08: FailUnimpl::edge32();
847 0x09: FailUnimpl::edge32n();
848 0x0A: FailUnimpl::edge32l();
849 0x0B: FailUnimpl::edge32ln();
850 0x10: FailUnimpl::array8();
851 0x12: FailUnimpl::array16();
852 0x14: FailUnimpl::array32();
853 0x18: BasicOperate::alignaddr({{
854 uint64_t sum = Rs1 + Rs2;
856 Gsr = (Gsr & ~7) | (sum & 7);
858 0x19: FailUnimpl::bmask();
859 0x1A: BasicOperate::alignaddresslittle({{
860 uint64_t sum = Rs1 + Rs2;
862 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
864 0x20: FailUnimpl::fcmple16();
865 0x22: FailUnimpl::fcmpne16();
866 0x24: FailUnimpl::fcmple32();
867 0x26: FailUnimpl::fcmpne32();
868 0x28: FailUnimpl::fcmpgt16();
869 0x2A: FailUnimpl::fcmpeq16();
870 0x2C: FailUnimpl::fcmpgt32();
871 0x2E: FailUnimpl::fcmpeq32();
872 0x31: FailUnimpl::fmul8x16();
873 0x33: FailUnimpl::fmul8x16au();
874 0x35: FailUnimpl::fmul8x16al();
875 0x36: FailUnimpl::fmul8sux16();
876 0x37: FailUnimpl::fmul8ulx16();
877 0x38: FailUnimpl::fmuld8sux16();
878 0x39: FailUnimpl::fmuld8ulx16();
879 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
880 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
881 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
882 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
883 0x48: BasicOperate::faligndata({{
884 uint64_t msbX = Frs1.udw;
885 uint64_t lsbX = Frs2.udw;
886 //Some special cases need to be split out, first
887 //because they're the most likely to be used, and
888 //second because otherwise, we end up shifting by
889 //greater than the width of the type being shifted,
890 //namely 64, which produces undefined results according
901 uint64_t msbShift = Gsr<2:0> * 8;
902 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
903 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
904 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
905 Frd.udw = ((msbX & msbMask) << msbShift) |
906 ((lsbX & lsbMask) >> lsbShift);
909 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
910 0x4C: FailUnimpl::bshuffle();
911 0x4D: FailUnimpl::fexpand();
912 0x50: FailUnimpl::fpadd16();
913 0x51: FailUnimpl::fpadd16s();
914 0x52: FailUnimpl::fpadd32();
915 0x53: FailUnimpl::fpadd32s();
916 0x54: FailUnimpl::fpsub16();
917 0x55: FailUnimpl::fpsub16s();
918 0x56: FailUnimpl::fpsub32();
919 0x57: FailUnimpl::fpsub32s();
920 0x60: FpBasic::fzero({{Frd.df = 0;}});
921 0x61: FpBasic::fzeros({{Frds.sf = 0;}});
922 0x62: FailUnimpl::fnor();
923 0x63: FailUnimpl::fnors();
924 0x64: FailUnimpl::fandnot2();
925 0x65: FailUnimpl::fandnot2s();
926 0x66: FpBasic::fnot2({{
927 Frd.df = (double)(~((uint64_t)Frs2.df));
929 0x67: FpBasic::fnot2s({{
930 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
932 0x68: FailUnimpl::fandnot1();
933 0x69: FailUnimpl::fandnot1s();
934 0x6A: FpBasic::fnot1({{
935 Frd.df = (double)(~((uint64_t)Frs1.df));
937 0x6B: FpBasic::fnot1s({{
938 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
940 0x6C: FailUnimpl::fxor();
941 0x6D: FailUnimpl::fxors();
942 0x6E: FailUnimpl::fnand();
943 0x6F: FailUnimpl::fnands();
944 0x70: FailUnimpl::fand();
945 0x71: FailUnimpl::fands();
946 0x72: FailUnimpl::fxnor();
947 0x73: FailUnimpl::fxnors();
948 0x74: FpBasic::fsrc1({{Frd.udw = Frs1.udw;}});
949 0x75: FpBasic::fsrc1s({{Frds.uw = Frs1s.uw;}});
950 0x76: FailUnimpl::fornot2();
951 0x77: FailUnimpl::fornot2s();
952 0x78: FpBasic::fsrc2({{Frd.udw = Frs2.udw;}});
953 0x79: FpBasic::fsrc2s({{Frds.uw = Frs2s.uw;}});
954 0x7A: FailUnimpl::fornot1();
955 0x7B: FailUnimpl::fornot1s();
956 0x7C: FailUnimpl::for();
957 0x7D: FailUnimpl::fors();
958 0x7E: FpBasic::fone({{Frd.udw = std::numeric_limits<uint64_t>::max();}});
959 0x7F: FpBasic::fones({{Frds.uw = std::numeric_limits<uint32_t>::max();}});
960 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
961 0x81: FailUnimpl::siam();
963 // M5 special opcodes use the reserved IMPDEP2A opcode space
964 0x37: decode M5FUNC {
966 format BasicOperate {
967 // we have 7 bits of space here to play with...
968 0x21: m5exit({{PseudoInst::m5exit(xc->tcBase(), O0);
969 }}, No_OpClass, IsNonSpeculative);
971 O0 = PseudoInst::readfile(xc->tcBase(), O0, O1, O2);
972 }}, IsNonSpeculative);
973 0x51: m5break({{PseudoInst::debugbreak(xc->tcBase());
974 }}, IsNonSpeculative);
976 panic("M5 panic instruction called at pc=%#x.", xc->readPC());
977 }}, No_OpClass, IsNonSpeculative);
980 default: Trap::impdep2({{fault = new IllegalInstruction;}});
982 0x38: Branch::jmpl({{
983 Addr target = Rs1 + Rs2_or_imm13;
985 fault = new MemAddressNotAligned;
989 Rd = (xc->readPC())<31:0>;
995 0x39: Branch::return({{
996 Addr target = Rs1 + Rs2_or_imm13;
999 //Check for fills which are higher priority than alignment
1004 fault = new FillNOther(4*Wstate<5:3>);
1006 fault = new FillNNormal(4*Wstate<2:0>);
1008 //Check for alignment faults
1009 else if(target & 0x3)
1010 fault = new MemAddressNotAligned;
1014 Cwp = (Cwp - 1 + NWindows) % NWindows;
1015 Cansave = Cansave + 1;
1016 Canrestore = Canrestore - 1;
1023 if(passesCondition(Ccr<3:0>, COND2))
1025 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1026 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1027 fault = new TrapInstruction(lTrapNum);
1029 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
1031 if(passesCondition(Ccr<7:4>, COND2))
1033 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
1034 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
1035 fault = new TrapInstruction(lTrapNum);
1037 }}, IsSerializeAfter, IsNonSpeculative, IsSyscall);
1039 0x3B: Nop::flush({{/*Instruction memory flush*/}}, IsWriteBarrier,
1045 fault = new SpillNOther(4*Wstate<5:3>);
1047 fault = new SpillNNormal(4*Wstate<2:0>);
1049 else if(Cleanwin - Canrestore == 0)
1051 fault = new CleanWindow;
1055 Cwp = (Cwp + 1) % NWindows;
1056 Rd_next = Rs1 + Rs2_or_imm13;
1057 Cansave = Cansave - 1;
1058 Canrestore = Canrestore + 1;
1065 fault = new FillNOther(4*Wstate<5:3>);
1067 fault = new FillNNormal(4*Wstate<2:0>);
1071 Cwp = (Cwp - 1 + NWindows) % NWindows;
1072 Rd_prev = Rs1 + Rs2_or_imm13;
1073 Cansave = Cansave + 1;
1074 Canrestore = Canrestore - 1;
1080 Pstate = Tstate<20:8>;
1081 Asi = Tstate<31:24>;
1082 Ccr = Tstate<39:32>;
1091 Pstate = Tstate<20:8>;
1092 Asi = Tstate<31:24>;
1093 Ccr = Tstate<39:32>;
1105 0x00: lduw({{Rd = Mem.uw;}});
1106 0x01: ldub({{Rd = Mem.ub;}});
1107 0x02: lduh({{Rd = Mem.uhw;}});
1109 RdLow = (Mem.tuw).a;
1110 RdHigh = (Mem.tuw).b;
1114 0x04: stw({{Mem.uw = Rd.sw;}});
1115 0x05: stb({{Mem.ub = Rd.sb;}});
1116 0x06: sth({{Mem.uhw = Rd.shw;}});
1118 //This temporary needs to be here so that the parser
1119 //will correctly identify this instruction as a store.
1120 //It's probably either the parenthesis or referencing
1121 //the member variable that throws confuses it.
1123 temp.a = RdLow<31:0>;
1124 temp.b = RdHigh<31:0>;
1129 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1130 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1131 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1132 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1134 0x0D: Swap::ldstub({{Mem.ub = 0xFF;}},
1136 uint8_t tmp = mem_data;
1139 0x0E: Store::stx({{Mem.udw = Rd}});
1140 0x0F: Swap::swap({{Mem.uw = Rd.uw}},
1142 uint32_t tmp = mem_data;
1146 0x10: lduwa({{Rd = Mem.uw;}});
1147 0x11: lduba({{Rd = Mem.ub;}});
1148 0x12: lduha({{Rd = Mem.uhw;}});
1149 0x13: decode EXT_ASI {
1151 0x22: TwinLoad::ldtx_aiup(
1152 {{RdLow.udw = (Mem.tudw).a;
1153 RdHigh.udw = (Mem.tudw).b;}});
1155 0x23: TwinLoad::ldtx_aius(
1156 {{RdLow.udw = (Mem.tudw).a;
1157 RdHigh.udw = (Mem.tudw).b;}});
1159 0x24: TwinLoad::ldtx_quad_ldd(
1160 {{RdLow.udw = (Mem.tudw).a;
1161 RdHigh.udw = (Mem.tudw).b;}});
1163 0x26: TwinLoad::ldtx_real(
1164 {{RdLow.udw = (Mem.tudw).a;
1165 RdHigh.udw = (Mem.tudw).b;}});
1167 0x27: TwinLoad::ldtx_n(
1168 {{RdLow.udw = (Mem.tudw).a;
1169 RdHigh.udw = (Mem.tudw).b;}});
1171 0x2A: TwinLoad::ldtx_aiup_l(
1172 {{RdLow.udw = (Mem.tudw).a;
1173 RdHigh.udw = (Mem.tudw).b;}});
1175 0x2B: TwinLoad::ldtx_aius_l(
1176 {{RdLow.udw = (Mem.tudw).a;
1177 RdHigh.udw = (Mem.tudw).b;}});
1179 0x2C: TwinLoad::ldtx_l(
1180 {{RdLow.udw = (Mem.tudw).a;
1181 RdHigh.udw = (Mem.tudw).b;}});
1183 0x2E: TwinLoad::ldtx_real_l(
1184 {{RdLow.udw = (Mem.tudw).a;
1185 RdHigh.udw = (Mem.tudw).b;}});
1187 0x2F: TwinLoad::ldtx_n_l(
1188 {{RdLow.udw = (Mem.tudw).a;
1189 RdHigh.udw = (Mem.tudw).b;}});
1191 0xE2: TwinLoad::ldtx_p(
1192 {{RdLow.udw = (Mem.tudw).a;
1193 RdHigh.udw = (Mem.tudw).b;}});
1195 0xE3: TwinLoad::ldtx_s(
1196 {{RdLow.udw = (Mem.tudw).a;
1197 RdHigh.udw = (Mem.tudw).b;}});
1199 0xEA: TwinLoad::ldtx_pl(
1200 {{RdLow.udw = (Mem.tudw).a;
1201 RdHigh.udw = (Mem.tudw).b;}});
1203 0xEB: TwinLoad::ldtx_sl(
1204 {{RdLow.udw = (Mem.tudw).a;
1205 RdHigh.udw = (Mem.tudw).b;}});
1207 RdLow = (Mem.tuw).a;
1208 RdHigh = (Mem.tuw).b;}});
1212 0x14: stwa({{Mem.uw = Rd;}});
1213 0x15: stba({{Mem.ub = Rd;}});
1214 0x16: stha({{Mem.uhw = Rd;}});
1216 //This temporary needs to be here so that the parser
1217 //will correctly identify this instruction as a store.
1218 //It's probably either the parenthesis or referencing
1219 //the member variable that throws confuses it.
1221 temp.a = RdLow<31:0>;
1222 temp.b = RdHigh<31:0>;
1227 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
1228 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
1229 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
1230 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
1232 0x1D: SwapAlt::ldstuba({{Mem.ub = 0xFF;}},
1234 uint8_t tmp = mem_data;
1237 0x1E: StoreAlt::stxa({{Mem.udw = Rd}});
1238 0x1F: SwapAlt::swapa({{Mem.uw = Rd.uw}},
1240 uint32_t tmp = mem_data;
1245 0x20: Load::ldf({{Frds.uw = Mem.uw;}});
1247 0x0: Load::ldfsr({{fault = checkFpEnableFault(xc);
1250 Fsr = Mem.uw | Fsr<63:32>;}});
1251 0x1: Load::ldxfsr({{fault = checkFpEnableFault(xc);
1255 default: FailUnimpl::ldfsrOther();
1257 0x22: ldqf({{fault = new FpDisabled;}});
1258 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1259 0x24: Store::stf({{Mem.uw = Frds.uw;}});
1261 0x0: StoreFsr::stfsr({{fault = checkFpEnableFault(xc);
1264 Mem.uw = Fsr<31:0>;}});
1265 0x1: StoreFsr::stxfsr({{fault = checkFpEnableFault(xc);
1269 default: FailUnimpl::stfsrOther();
1271 0x26: stqf({{fault = new FpDisabled;}});
1272 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1273 0x2D: Nop::prefetch({{ }});
1274 0x30: LoadAlt::ldfa({{Frds.uw = Mem.uw;}});
1275 0x32: ldqfa({{fault = new FpDisabled;}});
1277 0x33: decode EXT_ASI {
1279 0x04: FailUnimpl::lddfa_n();
1280 //ASI_NUCLEUS_LITTLE
1281 0x0C: FailUnimpl::lddfa_nl();
1282 //ASI_AS_IF_USER_PRIMARY
1283 0x10: FailUnimpl::lddfa_aiup();
1284 //ASI_AS_IF_USER_PRIMARY_LITTLE
1285 0x18: FailUnimpl::lddfa_aiupl();
1286 //ASI_AS_IF_USER_SECONDARY
1287 0x11: FailUnimpl::lddfa_aius();
1288 //ASI_AS_IF_USER_SECONDARY_LITTLE
1289 0x19: FailUnimpl::lddfa_aiusl();
1291 0x14: FailUnimpl::lddfa_real();
1293 0x1C: FailUnimpl::lddfa_real_l();
1295 0x15: FailUnimpl::lddfa_real_io();
1296 //ASI_REAL_IO_LITTLE
1297 0x1D: FailUnimpl::lddfa_real_io_l();
1299 0x80: FailUnimpl::lddfa_p();
1300 //ASI_PRIMARY_LITTLE
1301 0x88: FailUnimpl::lddfa_pl();
1303 0x81: FailUnimpl::lddfa_s();
1304 //ASI_SECONDARY_LITTLE
1305 0x89: FailUnimpl::lddfa_sl();
1306 //ASI_PRIMARY_NO_FAULT
1307 0x82: FailUnimpl::lddfa_pnf();
1308 //ASI_PRIMARY_NO_FAULT_LITTLE
1309 0x8A: FailUnimpl::lddfa_pnfl();
1310 //ASI_SECONDARY_NO_FAULT
1311 0x83: FailUnimpl::lddfa_snf();
1312 //ASI_SECONDARY_NO_FAULT_LITTLE
1313 0x8B: FailUnimpl::lddfa_snfl();
1317 //ASI_BLOCK_AS_IF_USER_PRIMARY
1318 0x16: FailUnimpl::ldblockf_aiup();
1319 //ASI_BLOCK_AS_IF_USER_SECONDARY
1320 0x17: FailUnimpl::ldblockf_aius();
1321 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1322 0x1E: FailUnimpl::ldblockf_aiupl();
1323 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1324 0x1F: FailUnimpl::ldblockf_aiusl();
1326 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
1327 //ASI_BLOCK_SECONDARY
1328 0xF1: FailUnimpl::ldblockf_s();
1329 //ASI_BLOCK_PRIMARY_LITTLE
1330 0xF8: FailUnimpl::ldblockf_pl();
1331 //ASI_BLOCK_SECONDARY_LITTLE
1332 0xF9: FailUnimpl::ldblockf_sl();
1337 0xD0: FailUnimpl::ldshortf_8p();
1339 0xD1: FailUnimpl::ldshortf_8s();
1340 //ASI_FL8_PRIMARY_LITTLE
1341 0xD8: FailUnimpl::ldshortf_8pl();
1342 //ASI_FL8_SECONDARY_LITTLE
1343 0xD9: FailUnimpl::ldshortf_8sl();
1345 0xD2: FailUnimpl::ldshortf_16p();
1346 //ASI_FL16_SECONDARY
1347 0xD3: FailUnimpl::ldshortf_16s();
1348 //ASI_FL16_PRIMARY_LITTLE
1349 0xDA: FailUnimpl::ldshortf_16pl();
1350 //ASI_FL16_SECONDARY_LITTLE
1351 0xDB: FailUnimpl::ldshortf_16sl();
1352 //Not an ASI which is legal with lddfa
1353 default: Trap::lddfa_bad_asi(
1354 {{fault = new DataAccessException;}});
1357 0x34: Store::stfa({{Mem.uw = Frds.uw;}});
1358 0x36: stqfa({{fault = new FpDisabled;}});
1360 0x37: decode EXT_ASI {
1362 0x04: FailUnimpl::stdfa_n();
1363 //ASI_NUCLEUS_LITTLE
1364 0x0C: FailUnimpl::stdfa_nl();
1365 //ASI_AS_IF_USER_PRIMARY
1366 0x10: FailUnimpl::stdfa_aiup();
1367 //ASI_AS_IF_USER_PRIMARY_LITTLE
1368 0x18: FailUnimpl::stdfa_aiupl();
1369 //ASI_AS_IF_USER_SECONDARY
1370 0x11: FailUnimpl::stdfa_aius();
1371 //ASI_AS_IF_USER_SECONDARY_LITTLE
1372 0x19: FailUnimpl::stdfa_aiusl();
1374 0x14: FailUnimpl::stdfa_real();
1376 0x1C: FailUnimpl::stdfa_real_l();
1378 0x15: FailUnimpl::stdfa_real_io();
1379 //ASI_REAL_IO_LITTLE
1380 0x1D: FailUnimpl::stdfa_real_io_l();
1382 0x80: FailUnimpl::stdfa_p();
1383 //ASI_PRIMARY_LITTLE
1384 0x88: FailUnimpl::stdfa_pl();
1386 0x81: FailUnimpl::stdfa_s();
1387 //ASI_SECONDARY_LITTLE
1388 0x89: FailUnimpl::stdfa_sl();
1389 //ASI_PRIMARY_NO_FAULT
1390 0x82: FailUnimpl::stdfa_pnf();
1391 //ASI_PRIMARY_NO_FAULT_LITTLE
1392 0x8A: FailUnimpl::stdfa_pnfl();
1393 //ASI_SECONDARY_NO_FAULT
1394 0x83: FailUnimpl::stdfa_snf();
1395 //ASI_SECONDARY_NO_FAULT_LITTLE
1396 0x8B: FailUnimpl::stdfa_snfl();
1400 //ASI_BLOCK_AS_IF_USER_PRIMARY
1401 0x16: FailUnimpl::stblockf_aiup();
1402 //ASI_BLOCK_AS_IF_USER_SECONDARY
1403 0x17: FailUnimpl::stblockf_aius();
1404 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1405 0x1E: FailUnimpl::stblockf_aiupl();
1406 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1407 0x1F: FailUnimpl::stblockf_aiusl();
1409 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1410 //ASI_BLOCK_SECONDARY
1411 0xF1: FailUnimpl::stblockf_s();
1412 //ASI_BLOCK_PRIMARY_LITTLE
1413 0xF8: FailUnimpl::stblockf_pl();
1414 //ASI_BLOCK_SECONDARY_LITTLE
1415 0xF9: FailUnimpl::stblockf_sl();
1420 0xD0: FailUnimpl::stshortf_8p();
1422 0xD1: FailUnimpl::stshortf_8s();
1423 //ASI_FL8_PRIMARY_LITTLE
1424 0xD8: FailUnimpl::stshortf_8pl();
1425 //ASI_FL8_SECONDARY_LITTLE
1426 0xD9: FailUnimpl::stshortf_8sl();
1428 0xD2: FailUnimpl::stshortf_16p();
1429 //ASI_FL16_SECONDARY
1430 0xD3: FailUnimpl::stshortf_16s();
1431 //ASI_FL16_PRIMARY_LITTLE
1432 0xDA: FailUnimpl::stshortf_16pl();
1433 //ASI_FL16_SECONDARY_LITTLE
1434 0xDB: FailUnimpl::stshortf_16sl();
1435 //Not an ASI which is legal with lddfa
1436 default: Trap::stdfa_bad_asi(
1437 {{fault = new DataAccessException;}});
1440 0x3C: CasAlt::casa({{
1441 mem_data = htog(Rs2.uw);
1444 uint32_t tmp = mem_data;
1447 0x3D: Nop::prefetcha({{ }});
1448 0x3E: CasAlt::casxa({{mem_data = gtoh(Rs2);
1449 Mem.udw = Rd.udw; }},
1450 {{ Rd.udw = mem_data; }}, MEM_SWAP_COND);