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Merge ktlim@zizzer:/bk/newmem
[gem5.git] / src / arch / sparc / isa / decoder.isa
1 // Copyright (c) 2006 The Regents of The University of Michigan
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
6 // met: redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer;
8 // redistributions in binary form must reproduce the above copyright
9 // notice, this list of conditions and the following disclaimer in the
10 // documentation and/or other materials provided with the distribution;
11 // neither the name of the copyright holders nor the names of its
12 // contributors may be used to endorse or promote products derived from
13 // this software without specific prior written permission.
14 //
15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 //
27 // Authors: Ali Saidi
28 // Gabe Black
29 // Steve Reinhardt
30
31 ////////////////////////////////////////////////////////////////////
32 //
33 // The actual decoder specification
34 //
35
36 decode OP default Unknown::unknown()
37 {
38 0x0: decode OP2
39 {
40 //Throw an illegal instruction acception
41 0x0: Trap::illtrap({{fault = new IllegalInstruction;}});
42 format BranchN
43 {
44 0x1: decode COND2
45 {
46 //Branch Always
47 0x8: decode A
48 {
49 0x0: b(19, {{
50 NNPC = xc->readPC() + disp;
51 }});
52 0x1: b(19, {{
53 NPC = xc->readPC() + disp;
54 NNPC = NPC + 4;
55 }}, ',a');
56 }
57 //Branch Never
58 0x0: decode A
59 {
60 0x0: bn(19, {{
61 NNPC = NNPC;//Don't do anything
62 }});
63 0x1: bn(19, {{
64 NPC = xc->readNextPC() + 4;
65 NNPC = NPC + 4;
66 }}, ',a');
67 }
68 default: decode BPCC
69 {
70 0x0: bpcci(19, {{
71 if(passesCondition(Ccr<3:0>, COND2))
72 NNPC = xc->readPC() + disp;
73 else
74 handle_annul
75 }});
76 0x2: bpccx(19, {{
77 if(passesCondition(Ccr<7:4>, COND2))
78 NNPC = xc->readPC() + disp;
79 else
80 handle_annul
81 }});
82 }
83 }
84 0x2: bicc(22, {{
85 if(passesCondition(Ccr<3:0>, COND2))
86 NNPC = xc->readPC() + disp;
87 else
88 handle_annul
89 }});
90 }
91 0x3: decode RCOND2
92 {
93 format BranchSplit
94 {
95 0x1: bpreq({{
96 if(Rs1.sdw == 0)
97 NNPC = xc->readPC() + disp;
98 else
99 handle_annul
100 }});
101 0x2: bprle({{
102 if(Rs1.sdw <= 0)
103 NNPC = xc->readPC() + disp;
104 else
105 handle_annul
106 }});
107 0x3: bprl({{
108 if(Rs1.sdw < 0)
109 NNPC = xc->readPC() + disp;
110 else
111 handle_annul
112 }});
113 0x5: bprne({{
114 if(Rs1.sdw != 0)
115 NNPC = xc->readPC() + disp;
116 else
117 handle_annul
118 }});
119 0x6: bprg({{
120 if(Rs1.sdw > 0)
121 NNPC = xc->readPC() + disp;
122 else
123 handle_annul
124 }});
125 0x7: bprge({{
126 if(Rs1.sdw >= 0)
127 NNPC = xc->readPC() + disp;
128 else
129 handle_annul
130 }});
131 }
132 }
133 //SETHI (or NOP if rd == 0 and imm == 0)
134 0x4: SetHi::sethi({{Rd.udw = imm;}});
135 0x5: Trap::fbpfcc({{fault = new FpDisabled;}});
136 0x6: Trap::fbfcc({{fault = new FpDisabled;}});
137 }
138 0x1: BranchN::call(30, {{
139 R15 = xc->readPC();
140 NNPC = R15 + disp;
141 }});
142 0x2: decode OP3 {
143 format IntOp {
144 0x00: add({{Rd = Rs1.sdw + Rs2_or_imm13;}});
145 0x01: and({{Rd = Rs1.sdw & Rs2_or_imm13;}});
146 0x02: or({{Rd = Rs1.sdw | Rs2_or_imm13;}});
147 0x03: xor({{Rd = Rs1.sdw ^ Rs2_or_imm13;}});
148 0x04: sub({{Rd = Rs1.sdw - Rs2_or_imm13;}});
149 0x05: andn({{Rd = Rs1.sdw & ~Rs2_or_imm13;}});
150 0x06: orn({{Rd = Rs1.sdw | ~Rs2_or_imm13;}});
151 0x07: xnor({{Rd = ~(Rs1.sdw ^ Rs2_or_imm13);}});
152 0x08: addc({{Rd = Rs1.sdw + Rs2_or_imm13 + Ccr<0:0>;}});
153 0x09: mulx({{Rd = Rs1.sdw * Rs2_or_imm13;}});
154 0x0A: umul({{
155 Rd = Rs1.udw<31:0> * Rs2_or_imm13<31:0>;
156 Y = Rd<63:32>;
157 }});
158 0x0B: smul({{
159 Rd.sdw = Rs1.sdw<31:0> * Rs2_or_imm13<31:0>;
160 Y = Rd.sdw;
161 }});
162 0x0C: subc({{Rd.sdw = Rs1.sdw + (~Rs2_or_imm13) + 1 - Ccr<0:0>}});
163 0x0D: udivx({{
164 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
165 else Rd.udw = Rs1.udw / Rs2_or_imm13;
166 }});
167 0x0E: udiv({{
168 if(Rs2_or_imm13 == 0) fault = new DivisionByZero;
169 else
170 {
171 Rd.udw = ((Y << 32) | Rs1.udw<31:0>) / Rs2_or_imm13;
172 if(Rd.udw >> 32 != 0)
173 Rd.udw = 0xFFFFFFFF;
174 }
175 }});
176 0x0F: sdiv({{
177 if(Rs2_or_imm13.sdw == 0)
178 fault = new DivisionByZero;
179 else
180 {
181 Rd.udw = ((int64_t)((Y << 32) | Rs1.sdw<31:0>)) / Rs2_or_imm13.sdw;
182 if(Rd.udw<63:31> != 0)
183 Rd.udw = 0x7FFFFFFF;
184 else if(Rd.udw<63:> && Rd.udw<62:31> != 0xFFFFFFFF)
185 Rd.udw = 0xFFFFFFFF80000000ULL;
186 }
187 }});
188 }
189 format IntOpCc {
190 0x10: addcc({{
191 int64_t resTemp, val2 = Rs2_or_imm13;
192 Rd = resTemp = Rs1 + val2;}},
193 {{(Rs1<31:0> + val2<31:0>)<32:>}},
194 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
195 {{(Rs1<63:1> + val2<63:1> + (Rs1 & val2)<0:>)<63:>}},
196 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
197 );
198 0x11: IntOpCcRes::andcc({{Rd = Rs1 & Rs2_or_imm13;}});
199 0x12: IntOpCcRes::orcc({{Rd = Rs1 | Rs2_or_imm13;}});
200 0x13: IntOpCcRes::xorcc({{Rd = Rs1 ^ Rs2_or_imm13;}});
201 0x14: subcc({{
202 int64_t val2 = Rs2_or_imm13;
203 Rd = Rs1 - val2;}},
204 {{(~(Rs1<31:0> + (~val2)<31:0> + 1))<32:>}},
205 {{(Rs1<31:> != val2<31:>) && (Rs1<31:> != Rd<31:>)}},
206 {{(~(Rs1<63:1> + (~val2)<63:1> +
207 (Rs1 | ~val2)<0:>))<63:>}},
208 {{Rs1<63:> != val2<63:> && Rs1<63:> != Rd<63:>}}
209 );
210 0x15: IntOpCcRes::andncc({{Rd = Rs1 & ~Rs2_or_imm13;}});
211 0x16: IntOpCcRes::orncc({{Rd = Rs1 | ~Rs2_or_imm13;}});
212 0x17: IntOpCcRes::xnorcc({{Rd = ~(Rs1 ^ Rs2_or_imm13);}});
213 0x18: addccc({{
214 int64_t resTemp, val2 = Rs2_or_imm13;
215 int64_t carryin = Ccr<0:0>;
216 Rd = resTemp = Rs1 + val2 + carryin;}},
217 {{(Rs1<31:0> + val2<31:0> + carryin)<32:>}},
218 {{Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>}},
219 {{(Rs1<63:1> + val2<63:1> +
220 ((Rs1 & val2) | (carryin & (Rs1 | val2)))<0:>)<63:>}},
221 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
222 );
223 0x1A: umulcc({{
224 uint64_t resTemp;
225 Rd = resTemp = Rs1.udw<31:0> * Rs2_or_imm13.udw<31:0>;
226 Y = resTemp<63:32>;}},
227 {{0}},{{0}},{{0}},{{0}});
228 0x1B: smulcc({{
229 int64_t resTemp;
230 Rd = resTemp = Rs1.sdw<31:0> * Rs2_or_imm13.sdw<31:0>;
231 Y = resTemp<63:32>;}},
232 {{0}},{{0}},{{0}},{{0}});
233 0x1C: subccc({{
234 int64_t resTemp, val2 = Rs2_or_imm13;
235 int64_t carryin = Ccr<0:0>;
236 Rd = resTemp = Rs1 + ~val2 + 1 - carryin;}},
237 {{(~((Rs1<31:0> + (~(val2 + carryin))<31:0> + 1))<32:>)}},
238 {{Rs1<31:> != val2<31:> && Rs1<31:> != resTemp<31:>}},
239 {{(~((Rs1<63:1> + (~(val2 + carryin))<63:1>) + (Rs1<0:> + (~(val2+carryin))<0:> + 1)<63:1>))<63:>}},
240 {{Rs1<63:> != val2<63:> && Rs1<63:> != resTemp<63:>}}
241 );
242 0x1D: udivxcc({{
243 if(Rs2_or_imm13.udw == 0) fault = new DivisionByZero;
244 else Rd = Rs1.udw / Rs2_or_imm13.udw;}}
245 ,{{0}},{{0}},{{0}},{{0}});
246 0x1E: udivcc({{
247 uint32_t resTemp, val2 = Rs2_or_imm13.udw;
248 int32_t overflow = 0;
249 if(val2 == 0) fault = new DivisionByZero;
250 else
251 {
252 resTemp = (uint64_t)((Y << 32) | Rs1.udw<31:0>) / val2;
253 overflow = (resTemp<63:32> != 0);
254 if(overflow) Rd = resTemp = 0xFFFFFFFF;
255 else Rd = resTemp;
256 } }},
257 {{0}},
258 {{overflow}},
259 {{0}},
260 {{0}}
261 );
262 0x1F: sdivcc({{
263 int64_t val2 = Rs2_or_imm13.sdw<31:0>;
264 bool overflow = false, underflow = false;
265 if(val2 == 0) fault = new DivisionByZero;
266 else
267 {
268 Rd = (int64_t)((Y << 32) | Rs1.sdw<31:0>) / val2;
269 overflow = (Rd<63:31> != 0);
270 underflow = (Rd<63:> && Rd<62:31> != 0xFFFFFFFF);
271 if(overflow) Rd = 0x7FFFFFFF;
272 else if(underflow) Rd = 0xFFFFFFFF80000000ULL;
273 } }},
274 {{0}},
275 {{overflow || underflow}},
276 {{0}},
277 {{0}}
278 );
279 0x20: taddcc({{
280 int64_t resTemp, val2 = Rs2_or_imm13;
281 Rd = resTemp = Rs1 + val2;
282 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
283 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
284 {{overflow}},
285 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
286 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
287 );
288 0x21: tsubcc({{
289 int64_t resTemp, val2 = Rs2_or_imm13;
290 Rd = resTemp = Rs1 + val2;
291 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);}},
292 {{(Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31}},
293 {{overflow}},
294 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
295 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
296 );
297 0x22: taddcctv({{
298 int64_t val2 = Rs2_or_imm13;
299 Rd = Rs1 + val2;
300 int32_t overflow = Rs1<1:0> || val2<1:0> ||
301 (Rs1<31:> == val2<31:> && val2<31:> != Rd<31:>);
302 if(overflow) fault = new TagOverflow;}},
303 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
304 {{overflow}},
305 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
306 {{Rs1<63:> == val2<63:> && val2<63:> != Rd<63:>}}
307 );
308 0x23: tsubcctv({{
309 int64_t resTemp, val2 = Rs2_or_imm13;
310 Rd = resTemp = Rs1 + val2;
311 int32_t overflow = Rs1<1:0> || val2<1:0> || (Rs1<31:> == val2<31:> && val2<31:> != resTemp<31:>);
312 if(overflow) fault = new TagOverflow;}},
313 {{((Rs1 & 0xFFFFFFFF + val2 & 0xFFFFFFFF) >> 31)}},
314 {{overflow}},
315 {{((Rs1 >> 1) + (val2 >> 1) + (Rs1 & val2 & 0x1))<63:>}},
316 {{Rs1<63:> == val2<63:> && val2<63:> != resTemp<63:>}}
317 );
318 0x24: mulscc({{
319 int64_t resTemp, multiplicand = Rs2_or_imm13;
320 int32_t multiplier = Rs1<31:0>;
321 int32_t savedLSB = Rs1<0:>;
322 multiplier = multiplier<31:1> |
323 ((Ccr<3:3>
324 ^ Ccr<1:1>) << 32);
325 if(!Y<0:>)
326 multiplicand = 0;
327 Rd = resTemp = multiplicand + multiplier;
328 Y = Y<31:1> | (savedLSB << 31);}},
329 {{((multiplicand & 0xFFFFFFFF + multiplier & 0xFFFFFFFF) >> 31)}},
330 {{multiplicand<31:> == multiplier<31:> && multiplier<31:> != resTemp<31:>}},
331 {{((multiplicand >> 1) + (multiplier >> 1) + (multiplicand & multiplier & 0x1))<63:>}},
332 {{multiplicand<63:> == multiplier<63:> && multiplier<63:> != resTemp<63:>}}
333 );
334 }
335 format IntOp
336 {
337 0x25: decode X {
338 0x0: sll({{Rd = Rs1 << (I ? SHCNT32 : Rs2<4:0>);}});
339 0x1: sllx({{Rd = Rs1 << (I ? SHCNT64 : Rs2<5:0>);}});
340 }
341 0x26: decode X {
342 0x0: srl({{Rd = Rs1.uw >> (I ? SHCNT32 : Rs2<4:0>);}});
343 0x1: srlx({{Rd = Rs1.udw >> (I ? SHCNT64 : Rs2<5:0>);}});
344 }
345 0x27: decode X {
346 0x0: sra({{Rd = Rs1.sw >> (I ? SHCNT32 : Rs2<4:0>);}});
347 0x1: srax({{Rd = Rs1.sdw >> (I ? SHCNT64 : Rs2<5:0>);}});
348 }
349 0x28: decode RS1 {
350 0x00: NoPriv::rdy({{Rd = Y;}});
351 //1 should cause an illegal instruction exception
352 0x02: NoPriv::rdccr({{Rd = Ccr;}});
353 0x03: NoPriv::rdasi({{Rd = Asi;}});
354 0x04: PrivCheck::rdtick({{Rd = Tick;}}, {{Tick<63:>}});
355 0x05: NoPriv::rdpc({{
356 if(Pstate<3:>)
357 Rd = (xc->readPC())<31:0>;
358 else
359 Rd = xc->readPC();}});
360 0x06: NoPriv::rdfprs({{
361 //Wait for all fpops to finish.
362 Rd = Fprs;
363 }});
364 //7-14 should cause an illegal instruction exception
365 0x0F: decode I {
366 0x0: Nop::stbar({{/*stuff*/}});
367 0x1: Nop::membar({{/*stuff*/}});
368 }
369 0x10: Priv::rdpcr({{Rd = Pcr;}});
370 0x11: PrivCheck::rdpic({{Rd = Pic;}}, {{Pcr<0:>}});
371 //0x12 should cause an illegal instruction exception
372 0x13: NoPriv::rdgsr({{
373 if(Fprs<2:> == 0 || Pstate<4:> == 0)
374 Rd = Gsr;
375 else
376 fault = new FpDisabled;
377 }});
378 //0x14-0x15 should cause an illegal instruction exception
379 0x16: Priv::rdsoftint({{Rd = Softint;}});
380 0x17: Priv::rdtick_cmpr({{Rd = TickCmpr;}});
381 0x18: PrivCheck::rdstick({{Rd = Stick}}, {{Stick<63:>}});
382 0x19: Priv::rdstick_cmpr({{Rd = StickCmpr;}});
383 //0x1A-0x1F should cause an illegal instruction exception
384 }
385 0x29: decode RS1 {
386 0x00: HPriv::rdhprhpstate({{Rd = Hpstate;}});
387 0x01: HPriv::rdhprhtstate({{
388 if(Tl == 0)
389 return new IllegalInstruction;
390 Rd = Htstate;
391 }});
392 //0x02 should cause an illegal instruction exception
393 0x03: HPriv::rdhprhintp({{Rd = Hintp;}});
394 //0x04 should cause an illegal instruction exception
395 0x05: HPriv::rdhprhtba({{Rd = Htba;}});
396 0x06: HPriv::rdhprhver({{Rd = Hver;}});
397 //0x07-0x1E should cause an illegal instruction exception
398 0x1F: HPriv::rdhprhstick_cmpr({{Rd = HstickCmpr;}});
399 }
400 0x2A: decode RS1 {
401 0x00: Priv::rdprtpc({{
402 if(Tl == 0)
403 return new IllegalInstruction;
404 Rd = Tpc;
405 }});
406 0x01: Priv::rdprtnpc({{
407 if(Tl == 0)
408 return new IllegalInstruction;
409 Rd = Tnpc;
410 }});
411 0x02: Priv::rdprtstate({{
412 if(Tl == 0)
413 return new IllegalInstruction;
414 Rd = Tstate;
415 }});
416 0x03: Priv::rdprtt({{
417 if(Tl == 0)
418 return new IllegalInstruction;
419 Rd = Tt;
420 }});
421 0x04: Priv::rdprtick({{Rd = Tick;}});
422 0x05: Priv::rdprtba({{Rd = Tba;}});
423 0x06: Priv::rdprpstate({{Rd = Pstate;}});
424 0x07: Priv::rdprtl({{Rd = Tl;}});
425 0x08: Priv::rdprpil({{Rd = Pil;}});
426 0x09: Priv::rdprcwp({{Rd = Cwp;}});
427 0x0A: Priv::rdprcansave({{Rd = Cansave;}});
428 0x0B: Priv::rdprcanrestore({{Rd = Canrestore;}});
429 0x0C: Priv::rdprcleanwin({{Rd = Cleanwin;}});
430 0x0D: Priv::rdprotherwin({{Rd = Otherwin;}});
431 0x0E: Priv::rdprwstate({{Rd = Wstate;}});
432 //0x0F should cause an illegal instruction exception
433 0x10: Priv::rdprgl({{Rd = Gl;}});
434 //0x11-0x1F should cause an illegal instruction exception
435 }
436 0x2B: BasicOperate::flushw({{
437 if(NWindows - 2 - Cansave == 0)
438 {
439 if(Otherwin)
440 fault = new SpillNOther(Wstate<5:3>);
441 else
442 fault = new SpillNNormal(Wstate<2:0>);
443 }
444 }});
445 0x2C: decode MOVCC3
446 {
447 0x0: Trap::movccfcc({{fault = new FpDisabled;}});
448 0x1: decode CC
449 {
450 0x0: movcci({{
451 if(passesCondition(Ccr<3:0>, COND4))
452 Rd = Rs2_or_imm11;
453 else
454 Rd = Rd;
455 }});
456 0x2: movccx({{
457 if(passesCondition(Ccr<7:4>, COND4))
458 Rd = Rs2_or_imm11;
459 else
460 Rd = Rd;
461 }});
462 }
463 }
464 0x2D: sdivx({{
465 if(Rs2_or_imm13.sdw == 0) fault = new DivisionByZero;
466 else Rd.sdw = Rs1.sdw / Rs2_or_imm13.sdw;
467 }});
468 0x2E: decode RS1 {
469 0x0: IntOp::popc({{
470 int64_t count = 0;
471 uint64_t temp = Rs2_or_imm13;
472 //Count the 1s in the front 4bits until none are left
473 uint8_t oneBits[] = {0,1,1,2,1,2,2,3,1,2,2,3,2,3,3,4};
474 while(temp)
475 {
476 count += oneBits[temp & 0xF];
477 temp = temp >> 4;
478 }
479 Rd = count;
480 }});
481 }
482 0x2F: decode RCOND3
483 {
484 0x1: movreq({{Rd = (Rs1.sdw == 0) ? Rs2_or_imm10 : Rd;}});
485 0x2: movrle({{Rd = (Rs1.sdw <= 0) ? Rs2_or_imm10 : Rd;}});
486 0x3: movrl({{Rd = (Rs1.sdw < 0) ? Rs2_or_imm10 : Rd;}});
487 0x5: movrne({{Rd = (Rs1.sdw != 0) ? Rs2_or_imm10 : Rd;}});
488 0x6: movrg({{Rd = (Rs1.sdw > 0) ? Rs2_or_imm10 : Rd;}});
489 0x7: movrge({{Rd = (Rs1.sdw >= 0) ? Rs2_or_imm10 : Rd;}});
490 }
491 0x30: decode RD {
492 0x00: NoPriv::wry({{Y = Rs1 ^ Rs2_or_imm13;}});
493 //0x01 should cause an illegal instruction exception
494 0x02: NoPriv::wrccr({{Ccr = Rs1 ^ Rs2_or_imm13;}});
495 0x03: NoPriv::wrasi({{Ccr = Rs1 ^ Rs2_or_imm13;}});
496 //0x04-0x05 should cause an illegal instruction exception
497 0x06: NoPriv::wrfprs({{Fprs = Rs1 ^ Rs2_or_imm13;}});
498 //0x07-0x0E should cause an illegal instruction exception
499 0x0F: Trap::softreset({{fault = new SoftwareInitiatedReset;}});
500 0x10: Priv::wrpcr({{Pcr = Rs1 ^ Rs2_or_imm13;}});
501 0x11: PrivCheck::wrpic({{Pic = Rs1 ^ Rs2_or_imm13;}}, {{Pcr<0:>}});
502 //0x12 should cause an illegal instruction exception
503 0x13: NoPriv::wrgsr({{
504 if(Fprs<2:> == 0 || Pstate<4:> == 0)
505 return new FpDisabled;
506 Gsr = Rs1 ^ Rs2_or_imm13;
507 }});
508 0x14: Priv::wrsoftint_set({{SoftintSet = Rs1 ^ Rs2_or_imm13;}});
509 0x15: Priv::wrsoftint_clr({{SoftintClr = Rs1 ^ Rs2_or_imm13;}});
510 0x16: Priv::wrsoftint({{Softint = Rs1 ^ Rs2_or_imm13;}});
511 0x17: Priv::wrtick_cmpr({{TickCmpr = Rs1 ^ Rs2_or_imm13;}});
512 0x18: NoPriv::wrstick({{
513 if(!Hpstate<2:>)
514 return new IllegalInstruction;
515 Stick = Rs1 ^ Rs2_or_imm13;
516 }});
517 0x19: Priv::wrstick_cmpr({{StickCmpr = Rs1 ^ Rs2_or_imm13;}});
518 //0x1A-0x1F should cause an illegal instruction exception
519 }
520 0x31: decode FCN {
521 0x0: Priv::saved({{
522 assert(Cansave < NWindows - 2);
523 assert(Otherwin || Canrestore);
524 Cansave = Cansave + 1;
525 if(Otherwin == 0)
526 Canrestore = Canrestore - 1;
527 else
528 Otherwin = Otherwin - 1;
529 }});
530 0x1: BasicOperate::restored({{
531 assert(Cansave || Otherwin);
532 assert(Canrestore < NWindows - 2);
533 Canrestore = Canrestore + 1;
534 if(Otherwin == 0)
535 Cansave = Cansave - 1;
536 else
537 Otherwin = Otherwin - 1;
538 }});
539 }
540 0x32: decode RD {
541 0x00: Priv::wrprtpc({{
542 if(Tl == 0)
543 return new IllegalInstruction;
544 else
545 Tpc = Rs1 ^ Rs2_or_imm13;
546 }});
547 0x01: Priv::wrprtnpc({{
548 if(Tl == 0)
549 return new IllegalInstruction;
550 else
551 Tnpc = Rs1 ^ Rs2_or_imm13;
552 }});
553 0x02: Priv::wrprtstate({{
554 if(Tl == 0)
555 return new IllegalInstruction;
556 else
557 Tstate = Rs1 ^ Rs2_or_imm13;
558 }});
559 0x03: Priv::wrprtt({{
560 if(Tl == 0)
561 return new IllegalInstruction;
562 else
563 Tt = Rs1 ^ Rs2_or_imm13;
564 }});
565 0x04: HPriv::wrprtick({{Tick = Rs1 ^ Rs2_or_imm13;}});
566 0x05: Priv::wrprtba({{Tba = Rs1 ^ Rs2_or_imm13;}});
567 0x06: Priv::wrprpstate({{Pstate = Rs1 ^ Rs2_or_imm13;}});
568 0x07: Priv::wrprtl({{
569 if(Pstate<2:> && !Hpstate<2:>)
570 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPTL);
571 else
572 Tl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxTL);
573 }});
574 0x08: Priv::wrprpil({{Pil = Rs1 ^ Rs2_or_imm13;}});
575 0x09: Priv::wrprcwp({{Cwp = Rs1 ^ Rs2_or_imm13;}});
576 0x0A: Priv::wrprcansave({{Cansave = Rs1 ^ Rs2_or_imm13;}});
577 0x0B: Priv::wrprcanrestore({{Canrestore = Rs1 ^ Rs2_or_imm13;}});
578 0x0C: Priv::wrprcleanwin({{Cleanwin = Rs1 ^ Rs2_or_imm13;}});
579 0x0D: Priv::wrprotherwin({{Otherwin = Rs1 ^ Rs2_or_imm13;}});
580 0x0E: Priv::wrprwstate({{Wstate = Rs1 ^ Rs2_or_imm13;}});
581 //0x0F should cause an illegal instruction exception
582 0x10: Priv::wrprgl({{
583 if(Pstate<2:> && !Hpstate<2:>)
584 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxPGL);
585 else
586 Gl = std::min<uint64_t>(Rs1 ^ Rs2_or_imm13, MaxGL);
587 }});
588 //0x11-0x1F should cause an illegal instruction exception
589 }
590 0x33: decode RD {
591 0x00: HPriv::wrhprhpstate({{Hpstate = Rs1 ^ Rs2_or_imm13;}});
592 0x01: HPriv::wrhprhtstate({{
593 if(Tl == 0)
594 return new IllegalInstruction;
595 Htstate = Rs1 ^ Rs2_or_imm13;
596 }});
597 //0x02 should cause an illegal instruction exception
598 0x03: HPriv::wrhprhintp({{Hintp = Rs1 ^ Rs2_or_imm13;}});
599 //0x04 should cause an illegal instruction exception
600 0x05: HPriv::wrhprhtba({{Htba = Rs1 ^ Rs2_or_imm13;}});
601 //0x06-0x01D should cause an illegal instruction exception
602 0x1F: HPriv::wrhprhstick_cmpr({{HstickCmpr = Rs1 ^ Rs2_or_imm13;}});
603 }
604 0x34: decode OPF{
605 format BasicOperate{
606 0x01: fmovs({{
607 Frds.uw = Frs2s.uw;
608 //fsr.ftt = fsr.cexc = 0
609 Fsr &= ~(7 << 14);
610 Fsr &= ~(0x1F);
611 }});
612 0x02: fmovd({{
613 Frd.udw = Frs2.udw;
614 //fsr.ftt = fsr.cexc = 0
615 Fsr &= ~(7 << 14);
616 Fsr &= ~(0x1F);
617 }});
618 0x03: Trap::fmovq({{fault = new FpDisabled;}});
619 0x05: fnegs({{
620 Frds.uw = Frs2s.uw ^ (1UL << 31);
621 //fsr.ftt = fsr.cexc = 0
622 Fsr &= ~(7 << 14);
623 Fsr &= ~(0x1F);
624 }});
625 0x06: fnegd({{
626 Frd.udw = Frs2.udw ^ (1ULL << 63);
627 //fsr.ftt = fsr.cexc = 0
628 Fsr &= ~(7 << 14);
629 Fsr &= ~(0x1F);
630 }});
631 0x07: Trap::fnegq({{fault = new FpDisabled;}});
632 0x09: fabss({{
633 Frds.uw = ((1UL << 31) - 1) & Frs2s.uw;
634 //fsr.ftt = fsr.cexc = 0
635 Fsr &= ~(7 << 14);
636 Fsr &= ~(0x1F);
637 }});
638 0x0A: fabsd({{
639 Frd.udw = ((1ULL << 63) - 1) & Frs2.udw;
640 //fsr.ftt = fsr.cexc = 0
641 Fsr &= ~(7 << 14);
642 Fsr &= ~(0x1F);
643 }});
644 0x0B: Trap::fabsq({{fault = new FpDisabled;}});
645 0x29: fsqrts({{Frds.sf = sqrt(Frs2s.sf);}});
646 0x2A: fsqrtd({{Frd.df = sqrt(Frs2.df);}});
647 0x2B: Trap::fsqrtq({{fault = new FpDisabled;}});
648 0x41: fadds({{Frds.sf = Frs1s.sf + Frs2s.sf;}});
649 0x42: faddd({{Frd.df = Frs1.df + Frs2.df;}});
650 0x43: Trap::faddq({{fault = new FpDisabled;}});
651 0x45: fsubs({{Frds.sf = Frs1s.sf - Frs2s.sf;}});
652 0x46: fsubd({{Frd.df = Frs1.df - Frs2.df;}});
653 0x47: Trap::fsubq({{fault = new FpDisabled;}});
654 0x49: fmuls({{Frds.sf = Frs1s.sf * Frs2s.sf;}});
655 0x4A: fmuld({{Frd.df = Frs1.df * Frs2.df;}});
656 0x4B: Trap::fmulq({{fault = new FpDisabled;}});
657 0x4D: fdivs({{Frds.sf = Frs1s.sf / Frs2s.sf;}});
658 0x4E: fdivd({{Frd.df = Frs1.df / Frs2.df;}});
659 0x4F: Trap::fdivq({{fault = new FpDisabled;}});
660 0x69: fsmuld({{Frd.df = Frs1s.sf * Frs2s.sf;}});
661 0x6E: Trap::fdmulq({{fault = new FpDisabled;}});
662 0x81: fstox({{
663 Frd.df = (double)static_cast<int64_t>(Frs2s.sf);
664 }});
665 0x82: fdtox({{
666 Frd.df = (double)static_cast<int64_t>(Frs2.df);
667 }});
668 0x83: Trap::fqtox({{fault = new FpDisabled;}});
669 0x84: fxtos({{
670 Frds.sf = static_cast<float>((int64_t)Frs2.df);
671 }});
672 0x88: fxtod({{
673 Frd.df = static_cast<double>((int64_t)Frs2.df);
674 }});
675 0x8C: Trap::fxtoq({{fault = new FpDisabled;}});
676 0xC4: fitos({{
677 Frds.sf = static_cast<float>((int32_t)Frs2s.sf);
678 }});
679 0xC6: fdtos({{Frds.sf = Frs2.df;}});
680 0xC7: Trap::fqtos({{fault = new FpDisabled;}});
681 0xC8: fitod({{
682 Frd.df = static_cast<double>((int32_t)Frs2s.sf);
683 }});
684 0xC9: fstod({{Frd.df = Frs2s.sf;}});
685 0xCB: Trap::fqtod({{fault = new FpDisabled;}});
686 0xCC: Trap::fitoq({{fault = new FpDisabled;}});
687 0xCD: Trap::fstoq({{fault = new FpDisabled;}});
688 0xCE: Trap::fdtoq({{fault = new FpDisabled;}});
689 0xD1: fstoi({{
690 Frds.sf = (float)static_cast<int32_t>(Frs2s.sf);
691 }});
692 0xD2: fdtoi({{
693 Frds.sf = (float)static_cast<int32_t>(Frs2.df);
694 }});
695 0xD3: Trap::fqtoi({{fault = new FpDisabled;}});
696 default: Trap::fpop1({{fault = new FpDisabled;}});
697 }
698 }
699 0x35: Trap::fpop2({{fault = new FpDisabled;}});
700 //This used to be just impdep1, but now it's a whole bunch
701 //of instructions
702 0x36: decode OPF{
703 0x00: Trap::edge8({{fault = new IllegalInstruction;}});
704 0x01: Trap::edge8n({{fault = new IllegalInstruction;}});
705 0x02: Trap::edge8l({{fault = new IllegalInstruction;}});
706 0x03: Trap::edge8ln({{fault = new IllegalInstruction;}});
707 0x04: Trap::edge16({{fault = new IllegalInstruction;}});
708 0x05: Trap::edge16n({{fault = new IllegalInstruction;}});
709 0x06: Trap::edge16l({{fault = new IllegalInstruction;}});
710 0x07: Trap::edge16ln({{fault = new IllegalInstruction;}});
711 0x08: Trap::edge32({{fault = new IllegalInstruction;}});
712 0x09: Trap::edge32n({{fault = new IllegalInstruction;}});
713 0x0A: Trap::edge32l({{fault = new IllegalInstruction;}});
714 0x0B: Trap::edge32ln({{fault = new IllegalInstruction;}});
715 0x10: Trap::array8({{fault = new IllegalInstruction;}});
716 0x12: Trap::array16({{fault = new IllegalInstruction;}});
717 0x14: Trap::array32({{fault = new IllegalInstruction;}});
718 0x18: BasicOperate::alignaddr({{
719 uint64_t sum = Rs1 + Rs2;
720 Rd = sum & ~7;
721 Gsr = (Gsr & ~7) | (sum & 7);
722 }});
723 0x19: Trap::bmask({{fault = new IllegalInstruction;}});
724 0x1A: BasicOperate::alignaddresslittle({{
725 uint64_t sum = Rs1 + Rs2;
726 Rd = sum & ~7;
727 Gsr = (Gsr & ~7) | ((~sum + 1) & 7);
728 }});
729 0x20: Trap::fcmple16({{fault = new IllegalInstruction;}});
730 0x22: Trap::fcmpne16({{fault = new IllegalInstruction;}});
731 0x24: Trap::fcmple32({{fault = new IllegalInstruction;}});
732 0x26: Trap::fcmpne32({{fault = new IllegalInstruction;}});
733 0x28: Trap::fcmpgt16({{fault = new IllegalInstruction;}});
734 0x2A: Trap::fcmpeq16({{fault = new IllegalInstruction;}});
735 0x2C: Trap::fcmpgt32({{fault = new IllegalInstruction;}});
736 0x2E: Trap::fcmpeq32({{fault = new IllegalInstruction;}});
737 0x31: Trap::fmul8x16({{fault = new IllegalInstruction;}});
738 0x33: Trap::fmul8x16au({{fault = new IllegalInstruction;}});
739 0x35: Trap::fmul8x16al({{fault = new IllegalInstruction;}});
740 0x36: Trap::fmul8sux16({{fault = new IllegalInstruction;}});
741 0x37: Trap::fmul8ulx16({{fault = new IllegalInstruction;}});
742 0x38: Trap::fmuld8sux16({{fault = new IllegalInstruction;}});
743 0x39: Trap::fmuld8ulx16({{fault = new IllegalInstruction;}});
744 0x3A: Trap::fpack32({{fault = new IllegalInstruction;}});
745 0x3B: Trap::fpack16({{fault = new IllegalInstruction;}});
746 0x3D: Trap::fpackfix({{fault = new IllegalInstruction;}});
747 0x3E: Trap::pdist({{fault = new IllegalInstruction;}});
748 0x48: BasicOperate::faligndata({{
749 uint64_t msbX = Frs1.udw;
750 uint64_t lsbX = Frs2.udw;
751 //Some special cases need to be split out, first
752 //because they're the most likely to be used, and
753 //second because otherwise, we end up shifting by
754 //greater than the width of the type being shifted,
755 //namely 64, which produces undefined results according
756 //to the C standard.
757 switch(Gsr<2:0>)
758 {
759 case 0:
760 Frd.udw = msbX;
761 break;
762 case 8:
763 Frd.udw = lsbX;
764 break;
765 default:
766 uint64_t msbShift = Gsr<2:0> * 8;
767 uint64_t lsbShift = (8 - Gsr<2:0>) * 8;
768 uint64_t msbMask = ((uint64_t)(-1)) >> msbShift;
769 uint64_t lsbMask = ((uint64_t)(-1)) << lsbShift;
770 Frd.udw = ((msbX & msbMask) << msbShift) |
771 ((lsbX & lsbMask) >> lsbShift);
772 }
773 }});
774 0x4B: Trap::fpmerge({{fault = new IllegalInstruction;}});
775 0x4C: Trap::bshuffle({{fault = new IllegalInstruction;}});
776 0x4D: Trap::fexpand({{fault = new IllegalInstruction;}});
777 0x50: Trap::fpadd16({{fault = new IllegalInstruction;}});
778 0x51: Trap::fpadd16s({{fault = new IllegalInstruction;}});
779 0x52: Trap::fpadd32({{fault = new IllegalInstruction;}});
780 0x53: Trap::fpadd32s({{fault = new IllegalInstruction;}});
781 0x54: Trap::fpsub16({{fault = new IllegalInstruction;}});
782 0x55: Trap::fpsub16s({{fault = new IllegalInstruction;}});
783 0x56: Trap::fpsub32({{fault = new IllegalInstruction;}});
784 0x57: Trap::fpsub32s({{fault = new IllegalInstruction;}});
785 0x60: BasicOperate::fzero({{Frd.df = 0;}});
786 0x61: BasicOperate::fzeros({{Frds.sf = 0;}});
787 0x62: Trap::fnor({{fault = new IllegalInstruction;}});
788 0x63: Trap::fnors({{fault = new IllegalInstruction;}});
789 0x64: Trap::fandnot2({{fault = new IllegalInstruction;}});
790 0x65: Trap::fandnot2s({{fault = new IllegalInstruction;}});
791 0x66: BasicOperate::fnot2({{
792 Frd.df = (double)(~((uint64_t)Frs2.df));
793 }});
794 0x67: BasicOperate::fnot2s({{
795 Frds.sf = (float)(~((uint32_t)Frs2s.sf));
796 }});
797 0x68: Trap::fandnot1({{fault = new IllegalInstruction;}});
798 0x69: Trap::fandnot1s({{fault = new IllegalInstruction;}});
799 0x6A: BasicOperate::fnot1({{
800 Frd.df = (double)(~((uint64_t)Frs1.df));
801 }});
802 0x6B: BasicOperate::fnot1s({{
803 Frds.sf = (float)(~((uint32_t)Frs1s.sf));
804 }});
805 0x6C: Trap::fxor({{fault = new IllegalInstruction;}});
806 0x6D: Trap::fxors({{fault = new IllegalInstruction;}});
807 0x6E: Trap::fnand({{fault = new IllegalInstruction;}});
808 0x6F: Trap::fnands({{fault = new IllegalInstruction;}});
809 0x70: Trap::fand({{fault = new IllegalInstruction;}});
810 0x71: Trap::fands({{fault = new IllegalInstruction;}});
811 0x72: Trap::fxnor({{fault = new IllegalInstruction;}});
812 0x73: Trap::fxnors({{fault = new IllegalInstruction;}});
813 0x74: BasicOperate::fsrc1({{Frd.udw = Frs1.udw;}});
814 0x75: BasicOperate::fsrc1s({{Frd.uw = Frs1.uw;}});
815 0x76: Trap::fornot2({{fault = new IllegalInstruction;}});
816 0x77: Trap::fornot2s({{fault = new IllegalInstruction;}});
817 0x78: BasicOperate::fsrc2({{Frd.udw = Frs2.udw;}});
818 0x79: BasicOperate::fsrc2s({{Frd.uw = Frs2.uw;}});
819 0x7A: Trap::fornot1({{fault = new IllegalInstruction;}});
820 0x7B: Trap::fornot1s({{fault = new IllegalInstruction;}});
821 0x7C: Trap::for({{fault = new IllegalInstruction;}});
822 0x7D: Trap::fors({{fault = new IllegalInstruction;}});
823 0x7E: Trap::fone({{fault = new IllegalInstruction;}});
824 0x7F: Trap::fones({{fault = new IllegalInstruction;}});
825 0x80: Trap::shutdown({{fault = new IllegalInstruction;}});
826 0x81: Trap::siam({{fault = new IllegalInstruction;}});
827 }
828 0x37: Trap::impdep2({{fault = new IllegalInstruction;}});
829 0x38: Branch::jmpl({{
830 Addr target = Rs1 + Rs2_or_imm13;
831 if(target & 0x3)
832 fault = new MemAddressNotAligned;
833 else
834 {
835 Rd = xc->readPC();
836 NNPC = target;
837 }
838 }});
839 0x39: Branch::return({{
840 //If both MemAddressNotAligned and
841 //a fill trap happen, it's not clear
842 //which one should be returned.
843 Addr target = Rs1 + Rs2_or_imm13;
844 if(target & 0x3)
845 fault = new MemAddressNotAligned;
846 else
847 NNPC = target;
848 if(fault == NoFault)
849 {
850 if(Canrestore == 0)
851 {
852 if(Otherwin)
853 fault = new FillNOther(Wstate<5:3>);
854 else
855 fault = new FillNNormal(Wstate<2:0>);
856 }
857 else
858 {
859 //CWP should be set directly so that it always happens
860 //Also, this will allow writing to the new window and
861 //reading from the old one
862 Cwp = (Cwp - 1 + NWindows) % NWindows;
863 Cansave = Cansave + 1;
864 Canrestore = Canrestore - 1;
865 //This is here to make sure the CWP is written
866 //no matter what. This ensures that the results
867 //are written in the new window as well.
868 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
869 }
870 }
871 }});
872 0x3A: decode CC
873 {
874 0x0: Trap::tcci({{
875 if(passesCondition(Ccr<3:0>, COND2))
876 {
877 #if FULL_SYSTEM
878 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
879 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
880 fault = new TrapInstruction(lTrapNum);
881 #else
882 DPRINTF(Sparc, "The syscall number is %d\n", R1);
883 xc->syscall(R1);
884 #endif
885 }
886 }});
887 0x2: Trap::tccx({{
888 if(passesCondition(Ccr<7:4>, COND2))
889 {
890 #if FULL_SYSTEM
891 int lTrapNum = I ? (Rs1 + SW_TRAP) : (Rs1 + Rs2);
892 DPRINTF(Sparc, "The trap number is %d\n", lTrapNum);
893 fault = new TrapInstruction(lTrapNum);
894 #else
895 DPRINTF(Sparc, "The syscall number is %d\n", R1);
896 xc->syscall(R1);
897 #endif
898 }
899 }});
900 }
901 0x3B: Nop::flush({{/*Instruction memory flush*/}});
902 0x3C: save({{
903 //CWP should be set directly so that it always happens
904 //Also, this will allow writing to the new window and
905 //reading from the old one
906 if(Cansave == 0)
907 {
908 if(Otherwin)
909 fault = new SpillNOther(Wstate<5:3>);
910 else
911 fault = new SpillNNormal(Wstate<2:0>);
912 //Cwp = (Cwp + 2) % NWindows;
913 }
914 else if(Cleanwin - Canrestore == 0)
915 {
916 //Cwp = (Cwp + 1) % NWindows;
917 fault = new CleanWindow;
918 }
919 else
920 {
921 Cwp = (Cwp + 1) % NWindows;
922 Rd = Rs1 + Rs2_or_imm13;
923 Cansave = Cansave - 1;
924 Canrestore = Canrestore + 1;
925 //This is here to make sure the CWP is written
926 //no matter what. This ensures that the results
927 //are written in the new window as well.
928 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
929 }
930 }});
931 0x3D: restore({{
932 if(Canrestore == 0)
933 {
934 if(Otherwin)
935 fault = new FillNOther(Wstate<5:3>);
936 else
937 fault = new FillNNormal(Wstate<2:0>);
938 }
939 else
940 {
941 //CWP should be set directly so that it always happens
942 //Also, this will allow writing to the new window and
943 //reading from the old one
944 Cwp = (Cwp - 1 + NWindows) % NWindows;
945 Rd = Rs1 + Rs2_or_imm13;
946 Cansave = Cansave + 1;
947 Canrestore = Canrestore - 1;
948 //This is here to make sure the CWP is written
949 //no matter what. This ensures that the results
950 //are written in the new window as well.
951 xc->setMiscRegWithEffect(MISCREG_CWP, Cwp);
952 }
953 }});
954 0x3E: decode FCN {
955 0x0: Priv::done({{
956 if(Tl == 0)
957 return new IllegalInstruction;
958
959 Cwp = Tstate<4:0>;
960 Pstate = Tstate<20:8>;
961 Asi = Tstate<31:24>;
962 Ccr = Tstate<39:32>;
963 Gl = Tstate<42:40>;
964 NPC = Tnpc;
965 NNPC = Tnpc + 4;
966 Tl = Tl - 1;
967 }});
968 0x1: Priv::retry({{
969 if(Tl == 0)
970 return new IllegalInstruction;
971 Cwp = Tstate<4:0>;
972 Pstate = Tstate<20:8>;
973 Asi = Tstate<31:24>;
974 Ccr = Tstate<39:32>;
975 Gl = Tstate<42:40>;
976 NPC = Tpc;
977 NNPC = Tnpc;
978 Tl = Tl - 1;
979 }});
980 }
981 }
982 }
983 0x3: decode OP3 {
984 format Load {
985 0x00: lduw({{Rd = Mem.uw;}});
986 0x01: ldub({{Rd = Mem.ub;}});
987 0x02: lduh({{Rd = Mem.uhw;}});
988 0x03: ldd({{
989 uint64_t val = Mem.udw;
990 RdLow = val<31:0>;
991 RdHigh = val<63:32>;
992 }});
993 }
994 format Store {
995 0x04: stw({{Mem.uw = Rd.sw;}});
996 0x05: stb({{Mem.ub = Rd.sb;}});
997 0x06: sth({{Mem.uhw = Rd.shw;}});
998 0x07: std({{Mem.udw = RdLow<31:0> | (RdHigh<31:0> << 32);}});
999 }
1000 format Load {
1001 0x08: ldsw({{Rd = (int32_t)Mem.sw;}});
1002 0x09: ldsb({{Rd = (int8_t)Mem.sb;}});
1003 0x0A: ldsh({{Rd = (int16_t)Mem.shw;}});
1004 0x0B: ldx({{Rd = (int64_t)Mem.sdw;}});
1005 }
1006 0x0D: LoadStore::ldstub(
1007 {{Rd = Mem.ub;}},
1008 {{Mem.ub = 0xFF;}});
1009 0x0E: Store::stx({{Mem.udw = Rd}});
1010 0x0F: LoadStore::swap(
1011 {{uReg0 = Rd.uw;
1012 Rd.uw = Mem.uw;}},
1013 {{Mem.uw = uReg0;}});
1014 format Load {
1015 0x10: lduwa({{Rd = Mem.uw;}});
1016 0x11: lduba({{Rd = Mem.ub;}});
1017 0x12: lduha({{Rd = Mem.uhw;}});
1018 0x13: ldda({{
1019 uint64_t val = Mem.udw;
1020 RdLow = val<31:0>;
1021 RdHigh = val<63:32>;
1022 }});
1023 }
1024 format Store {
1025 0x14: stwa({{Mem.uw = Rd;}});
1026 0x15: stba({{Mem.ub = Rd;}});
1027 0x16: stha({{Mem.uhw = Rd;}});
1028 0x17: stda({{Mem.udw = RdLow<31:0> | RdHigh<31:0> << 32;}});
1029 }
1030 format Load {
1031 0x18: ldswa({{Rd = (int32_t)Mem.sw;}});
1032 0x19: ldsba({{Rd = (int8_t)Mem.sb;}});
1033 0x1A: ldsha({{Rd = (int16_t)Mem.shw;}});
1034 0x1B: ldxa({{Rd = (int64_t)Mem.sdw;}});
1035 }
1036 0x1D: LoadStore::ldstuba(
1037 {{Rd = Mem.ub;}},
1038 {{Mem.ub = 0xFF}});
1039 0x1E: Store::stxa({{Mem.udw = Rd}});
1040 0x1F: LoadStore::swapa(
1041 {{uReg0 = Rd.uw;
1042 Rd.uw = Mem.uw;}},
1043 {{Mem.uw = uReg0;}});
1044 format Trap {
1045 0x20: Load::ldf({{Frd.uw = Mem.uw;}});
1046 0x21: decode X {
1047 0x0: Load::ldfsr({{Fsr = Mem.uw | Fsr<63:32>;}});
1048 0x1: Load::ldxfsr({{Fsr = Mem.udw;}});
1049 }
1050 0x22: ldqf({{fault = new FpDisabled;}});
1051 0x23: Load::lddf({{Frd.udw = Mem.udw;}});
1052 0x24: Store::stf({{Mem.uw = Frd.uw;}});
1053 0x25: decode X {
1054 0x0: Store::stfsr({{Mem.uw = Fsr<31:0>;}});
1055 0x1: Store::stxfsr({{Mem.udw = Fsr;}});
1056 }
1057 0x26: stqf({{fault = new FpDisabled;}});
1058 0x27: Store::stdf({{Mem.udw = Frd.udw;}});
1059 0x2D: Nop::prefetch({{ }});
1060 0x30: Load::ldfa({{Frd.uw = Mem.uw;}});
1061 0x32: ldqfa({{fault = new FpDisabled;}});
1062 format LoadAlt {
1063 0x33: decode EXT_ASI {
1064 //ASI_NUCLEUS
1065 0x04: FailUnimpl::lddfa_n();
1066 //ASI_NUCLEUS_LITTLE
1067 0x0C: FailUnimpl::lddfa_nl();
1068 //ASI_AS_IF_USER_PRIMARY
1069 0x10: FailUnimpl::lddfa_aiup();
1070 //ASI_AS_IF_USER_PRIMARY_LITTLE
1071 0x18: FailUnimpl::lddfa_aiupl();
1072 //ASI_AS_IF_USER_SECONDARY
1073 0x11: FailUnimpl::lddfa_aius();
1074 //ASI_AS_IF_USER_SECONDARY_LITTLE
1075 0x19: FailUnimpl::lddfa_aiusl();
1076 //ASI_REAL
1077 0x14: FailUnimpl::lddfa_real();
1078 //ASI_REAL_LITTLE
1079 0x1C: FailUnimpl::lddfa_real_l();
1080 //ASI_REAL_IO
1081 0x15: FailUnimpl::lddfa_real_io();
1082 //ASI_REAL_IO_LITTLE
1083 0x1D: FailUnimpl::lddfa_real_io_l();
1084 //ASI_PRIMARY
1085 0x80: FailUnimpl::lddfa_p();
1086 //ASI_PRIMARY_LITTLE
1087 0x88: FailUnimpl::lddfa_pl();
1088 //ASI_SECONDARY
1089 0x81: FailUnimpl::lddfa_s();
1090 //ASI_SECONDARY_LITTLE
1091 0x89: FailUnimpl::lddfa_sl();
1092 //ASI_PRIMARY_NO_FAULT
1093 0x82: FailUnimpl::lddfa_pnf();
1094 //ASI_PRIMARY_NO_FAULT_LITTLE
1095 0x8A: FailUnimpl::lddfa_pnfl();
1096 //ASI_SECONDARY_NO_FAULT
1097 0x83: FailUnimpl::lddfa_snf();
1098 //ASI_SECONDARY_NO_FAULT_LITTLE
1099 0x8B: FailUnimpl::lddfa_snfl();
1100
1101 format BlockLoad {
1102 // LDBLOCKF
1103 //ASI_BLOCK_AS_IF_USER_PRIMARY
1104 0x16: FailUnimpl::ldblockf_aiup();
1105 //ASI_BLOCK_AS_IF_USER_SECONDARY
1106 0x17: FailUnimpl::ldblockf_aius();
1107 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1108 0x1E: FailUnimpl::ldblockf_aiupl();
1109 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1110 0x1F: FailUnimpl::ldblockf_aiusl();
1111 //ASI_BLOCK_PRIMARY
1112 0xF0: ldblockf_p({{Frd_N.udw = Mem.udw;}});
1113 //ASI_BLOCK_SECONDARY
1114 0xF1: FailUnimpl::ldblockf_s();
1115 //ASI_BLOCK_PRIMARY_LITTLE
1116 0xF8: FailUnimpl::ldblockf_pl();
1117 //ASI_BLOCK_SECONDARY_LITTLE
1118 0xF9: FailUnimpl::ldblockf_sl();
1119 }
1120
1121 //LDSHORTF
1122 //ASI_FL8_PRIMARY
1123 0xD0: FailUnimpl::ldshortf_8p();
1124 //ASI_FL8_SECONDARY
1125 0xD1: FailUnimpl::ldshortf_8s();
1126 //ASI_FL8_PRIMARY_LITTLE
1127 0xD8: FailUnimpl::ldshortf_8pl();
1128 //ASI_FL8_SECONDARY_LITTLE
1129 0xD9: FailUnimpl::ldshortf_8sl();
1130 //ASI_FL16_PRIMARY
1131 0xD2: FailUnimpl::ldshortf_16p();
1132 //ASI_FL16_SECONDARY
1133 0xD3: FailUnimpl::ldshortf_16s();
1134 //ASI_FL16_PRIMARY_LITTLE
1135 0xDA: FailUnimpl::ldshortf_16pl();
1136 //ASI_FL16_SECONDARY_LITTLE
1137 0xDB: FailUnimpl::ldshortf_16sl();
1138 //Not an ASI which is legal with lddfa
1139 default: Trap::lddfa_bad_asi(
1140 {{fault = new DataAccessException;}});
1141 }
1142 }
1143 0x34: Store::stfa({{Mem.uw = Frd.uw;}});
1144 0x36: stqfa({{fault = new FpDisabled;}});
1145 format StoreAlt {
1146 0x37: decode EXT_ASI {
1147 //ASI_NUCLEUS
1148 0x04: FailUnimpl::stdfa_n();
1149 //ASI_NUCLEUS_LITTLE
1150 0x0C: FailUnimpl::stdfa_nl();
1151 //ASI_AS_IF_USER_PRIMARY
1152 0x10: FailUnimpl::stdfa_aiup();
1153 //ASI_AS_IF_USER_PRIMARY_LITTLE
1154 0x18: FailUnimpl::stdfa_aiupl();
1155 //ASI_AS_IF_USER_SECONDARY
1156 0x11: FailUnimpl::stdfa_aius();
1157 //ASI_AS_IF_USER_SECONDARY_LITTLE
1158 0x19: FailUnimpl::stdfa_aiusl();
1159 //ASI_REAL
1160 0x14: FailUnimpl::stdfa_real();
1161 //ASI_REAL_LITTLE
1162 0x1C: FailUnimpl::stdfa_real_l();
1163 //ASI_REAL_IO
1164 0x15: FailUnimpl::stdfa_real_io();
1165 //ASI_REAL_IO_LITTLE
1166 0x1D: FailUnimpl::stdfa_real_io_l();
1167 //ASI_PRIMARY
1168 0x80: FailUnimpl::stdfa_p();
1169 //ASI_PRIMARY_LITTLE
1170 0x88: FailUnimpl::stdfa_pl();
1171 //ASI_SECONDARY
1172 0x81: FailUnimpl::stdfa_s();
1173 //ASI_SECONDARY_LITTLE
1174 0x89: FailUnimpl::stdfa_sl();
1175 //ASI_PRIMARY_NO_FAULT
1176 0x82: FailUnimpl::stdfa_pnf();
1177 //ASI_PRIMARY_NO_FAULT_LITTLE
1178 0x8A: FailUnimpl::stdfa_pnfl();
1179 //ASI_SECONDARY_NO_FAULT
1180 0x83: FailUnimpl::stdfa_snf();
1181 //ASI_SECONDARY_NO_FAULT_LITTLE
1182 0x8B: FailUnimpl::stdfa_snfl();
1183
1184 format BlockStore {
1185 // STBLOCKF
1186 //ASI_BLOCK_AS_IF_USER_PRIMARY
1187 0x16: FailUnimpl::stblockf_aiup();
1188 //ASI_BLOCK_AS_IF_USER_SECONDARY
1189 0x17: FailUnimpl::stblockf_aius();
1190 //ASI_BLOCK_AS_IF_USER_PRIMARY_LITTLE
1191 0x1E: FailUnimpl::stblockf_aiupl();
1192 //ASI_BLOCK_AS_IF_USER_SECONDARY_LITTLE
1193 0x1F: FailUnimpl::stblockf_aiusl();
1194 //ASI_BLOCK_PRIMARY
1195 0xF0: stblockf_p({{Mem.udw = Frd_N.udw;}});
1196 //ASI_BLOCK_SECONDARY
1197 0xF1: FailUnimpl::stblockf_s();
1198 //ASI_BLOCK_PRIMARY_LITTLE
1199 0xF8: FailUnimpl::stblockf_pl();
1200 //ASI_BLOCK_SECONDARY_LITTLE
1201 0xF9: FailUnimpl::stblockf_sl();
1202 }
1203
1204 //STSHORTF
1205 //ASI_FL8_PRIMARY
1206 0xD0: FailUnimpl::stshortf_8p();
1207 //ASI_FL8_SECONDARY
1208 0xD1: FailUnimpl::stshortf_8s();
1209 //ASI_FL8_PRIMARY_LITTLE
1210 0xD8: FailUnimpl::stshortf_8pl();
1211 //ASI_FL8_SECONDARY_LITTLE
1212 0xD9: FailUnimpl::stshortf_8sl();
1213 //ASI_FL16_PRIMARY
1214 0xD2: FailUnimpl::stshortf_16p();
1215 //ASI_FL16_SECONDARY
1216 0xD3: FailUnimpl::stshortf_16s();
1217 //ASI_FL16_PRIMARY_LITTLE
1218 0xDA: FailUnimpl::stshortf_16pl();
1219 //ASI_FL16_SECONDARY_LITTLE
1220 0xDB: FailUnimpl::stshortf_16sl();
1221 //Not an ASI which is legal with lddfa
1222 default: Trap::stdfa_bad_asi(
1223 {{fault = new DataAccessException;}});
1224 }
1225 }
1226 0x3C: Cas::casa(
1227 {{uReg0 = Mem.uw;}},
1228 {{if(Rs2.uw == uReg0)
1229 Mem.uw = Rd.uw;
1230 else
1231 storeCond = false;
1232 Rd.uw = uReg0;}});
1233 0x3D: Nop::prefetcha({{ }});
1234 0x3E: Cas::casxa(
1235 {{uReg0 = Mem.udw;}},
1236 {{if(Rs2 == uReg0)
1237 Mem.udw = Rd;
1238 else
1239 storeCond = false;
1240 Rd = uReg0;}});
1241 }
1242 }
1243 }