src/arch/sparc/isa/formats/mem/basicmem.isa

   1 // Copyright (c) 2006-2007 The Regents of The University of Michigan
   2 // All rights reserved.
   3 //
   4 // Redistribution and use in source and binary forms, with or without
   5 // modification, are permitted provided that the following conditions are
   6 // met: redistributions of source code must retain the above copyright
   7 // notice, this list of conditions and the following disclaimer;
   8 // redistributions in binary form must reproduce the above copyright
   9 // notice, this list of conditions and the following disclaimer in the
  10 // documentation and/or other materials provided with the distribution;
  11 // neither the name of the copyright holders nor the names of its
  12 // contributors may be used to endorse or promote products derived from
  13 // this software without specific prior written permission.
  14 //
  15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  26 //
  27 // Authors: Ali Saidi
  28 //          Gabe Black
  29
  30 ////////////////////////////////////////////////////////////////////
  31 //
  32 // Mem instructions
  33 //
  34
  35 def template MemDeclare {{
  36         /**
  37          * Static instruction class for "%(mnemonic)s".
  38          */
  39         class %(class_name)s : public %(base_class)s
  40         {
  41           public:
  42
  43             /// Constructor.
  44             %(class_name)s(ExtMachInst machInst);
  45
  46             %(BasicExecDeclare)s
  47
  48             %(InitiateAccDeclare)s
  49
  50             %(CompleteAccDeclare)s
  51         };
  52 }};
  53
  54 let {{
  55     def doMemFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
  56         addrCalcReg = 'EA = Rs1 + Rs2;'
  57         addrCalcImm = 'EA = Rs1 + imm;'
  58         iop = InstObjParams(name, Name, 'Mem',
  59                 {"code": code, "postacc_code" : postacc_code,
  60                  "fault_check": faultCode, "ea_code": addrCalcReg,
  61                  "EA_trunc": TruncateEA}, opt_flags)
  62         iop_imm = InstObjParams(name, Name + "Imm", 'MemImm',
  63                 {"code": code, "postacc_code" : postacc_code,
  64                  "fault_check": faultCode, "ea_code": addrCalcImm,
  65                  "EA_trunc": TruncateEA}, opt_flags)
  66         header_output = MemDeclare.subst(iop) + MemDeclare.subst(iop_imm)
  67         decoder_output = BasicConstructor.subst(iop) + BasicConstructor.subst(iop_imm)
  68         decode_block = ROrImmDecode.subst(iop)
  69         exec_output = doDualSplitExecute(code, postacc_code, addrCalcReg,
  70                 addrCalcImm, execute, faultCode, name, name + "Imm",
  71                 Name, Name + "Imm", asi, opt_flags)
  72         return (header_output, decoder_output, exec_output, decode_block)
  73 }};
  74
  75 def format LoadAlt(code, *opt_flags) {{
  76         code = filterDoubles(code)
  77         (header_output,
  78          decoder_output,
  79          exec_output,
  80          decode_block) = doMemFormat(code, LoadFuncs,
  81             AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
  82 }};
  83
  84 def format StoreAlt(code, *opt_flags) {{
  85         code = filterDoubles(code)
  86         (header_output,
  87          decoder_output,
  88          exec_output,
  89          decode_block) = doMemFormat(code, StoreFuncs,
  90             AlternateASIPrivFaultCheck, name, Name, "EXT_ASI", opt_flags)
  91 }};
  92
  93 def format Load(code, *opt_flags) {{
  94         code = filterDoubles(code)
  95         (header_output,
  96          decoder_output,
  97          exec_output,
  98          decode_block) = doMemFormat(code,
  99              LoadFuncs, '', name, Name, 0, opt_flags)
 100 }};
 101
 102 def format Store(code, *opt_flags) {{
 103         code = filterDoubles(code)
 104         (header_output,
 105          decoder_output,
 106          exec_output,
 107          decode_block) = doMemFormat(code,
 108              StoreFuncs, '', name, Name, 0, opt_flags)
 109 }};
 110
 111 def format StoreFsr(code, *opt_flags) {{
 112         code = filterDoubles(code)
 113         (header_output,
 114          decoder_output,
 115          exec_output,
 116          decode_block) = doMemFormat(code,
 117              StoreFuncs, '', name, Name, 0, opt_flags,
 118              'Fsr = insertBits(Fsr,16,14,0);')
 119 }};
 120
 121 def format TwinLoad(code, *opt_flags) {{
 122         (header_output,
 123          decoder_output,
 124          exec_output,
 125          decode_block) = doMemFormat(code, LoadFuncs,
 126             AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck,
 127             name, Name, "EXT_ASI", opt_flags)
 128 }};
 129