1 // Copyright (c) 2006-2007 The Regents of The University of Michigan
2 // All rights reserved.
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
6 // met: redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer;
8 // redistributions in binary form must reproduce the above copyright
9 // notice, this list of conditions and the following disclaimer in the
10 // documentation and/or other materials provided with the distribution;
11 // neither the name of the copyright holders nor the names of its
12 // contributors may be used to endorse or promote products derived from
13 // this software without specific prior written permission.
15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
30 ////////////////////////////////////////////////////////////////////
32 // Block Memory instructions
37 class BlockMem : public SparcMacroInst
42 // We make the assumption that all block memory operations
43 // Will take 8 instructions to execute
44 BlockMem(const char *mnem, ExtMachInst _machInst) :
45 SparcMacroInst(mnem, _machInst, No_OpClass, 8)
49 class BlockMemImm : public BlockMem
54 BlockMemImm(const char *mnem, ExtMachInst _machInst) :
55 BlockMem(mnem, _machInst)
59 class BlockMemMicro : public SparcMicroInst
64 BlockMemMicro(const char *mnem, ExtMachInst _machInst,
65 OpClass __opClass, int8_t _offset) :
66 SparcMicroInst(mnem, _machInst, __opClass),
70 std::string generateDisassembly(Addr pc,
71 const SymbolTable *symtab) const;
76 class BlockMemImmMicro : public BlockMemMicro
81 BlockMemImmMicro(const char *mnem, ExtMachInst _machInst,
82 OpClass __opClass, int8_t _offset) :
83 BlockMemMicro(mnem, _machInst, __opClass, _offset),
87 std::string generateDisassembly(Addr pc,
88 const SymbolTable *symtab) const;
96 class TwinMem : public SparcMacroInst
101 // We make the assumption that all block memory operations
102 // Will take 8 instructions to execute
103 TwinMem(const char *mnem, ExtMachInst _machInst) :
104 SparcMacroInst(mnem, _machInst, No_OpClass, 2)
108 class TwinMemImm : public BlockMem
113 TwinMemImm(const char *mnem, ExtMachInst _machInst) :
114 BlockMem(mnem, _machInst)
118 class TwinMemMicro : public SparcMicroInst
123 TwinMemMicro(const char *mnem, ExtMachInst _machInst,
124 OpClass __opClass, int8_t _offset) :
125 SparcMicroInst(mnem, _machInst, __opClass),
129 std::string generateDisassembly(Addr pc,
130 const SymbolTable *symtab) const;
135 class TwinMemImmMicro : public BlockMemMicro
140 TwinMemImmMicro(const char *mnem, ExtMachInst _machInst,
141 OpClass __opClass, int8_t _offset) :
142 BlockMemMicro(mnem, _machInst, __opClass, _offset),
143 imm(sext<13>(SIMM13))
146 std::string generateDisassembly(Addr pc,
147 const SymbolTable *symtab) const;
154 std::string BlockMemMicro::generateDisassembly(Addr pc,
155 const SymbolTable *symtab) const
157 std::stringstream response;
158 bool load = flags[IsLoad];
159 bool save = flags[IsStore];
161 printMnemonic(response, mnemonic);
164 printReg(response, _srcRegIdx[0]);
165 ccprintf(response, ", ");
167 ccprintf(response, "[ ");
168 printReg(response, _srcRegIdx[!save ? 0 : 1]);
169 ccprintf(response, " + ");
170 printReg(response, _srcRegIdx[!save ? 1 : 2]);
171 ccprintf(response, " ]");
174 ccprintf(response, ", ");
175 printReg(response, _destRegIdx[0]);
178 return response.str();
181 std::string BlockMemImmMicro::generateDisassembly(Addr pc,
182 const SymbolTable *symtab) const
184 std::stringstream response;
185 bool load = flags[IsLoad];
186 bool save = flags[IsStore];
188 printMnemonic(response, mnemonic);
191 printReg(response, _srcRegIdx[1]);
192 ccprintf(response, ", ");
194 ccprintf(response, "[ ");
195 printReg(response, _srcRegIdx[0]);
197 ccprintf(response, " + 0x%x ]", imm);
199 ccprintf(response, " + -0x%x ]", -imm);
202 ccprintf(response, ", ");
203 printReg(response, _destRegIdx[0]);
206 return response.str();
212 std::string TwinMemMicro::generateDisassembly(Addr pc,
213 const SymbolTable *symtab) const
215 std::stringstream response;
216 bool load = flags[IsLoad];
217 bool save = flags[IsStore];
219 printMnemonic(response, mnemonic);
222 printReg(response, _srcRegIdx[0]);
223 ccprintf(response, ", ");
225 ccprintf(response, "[ ");
226 printReg(response, _srcRegIdx[!save ? 0 : 1]);
227 ccprintf(response, " + ");
228 printReg(response, _srcRegIdx[!save ? 1 : 2]);
229 ccprintf(response, " ]");
232 ccprintf(response, ", ");
233 printReg(response, _destRegIdx[0]);
236 return response.str();
239 std::string TwinMemImmMicro::generateDisassembly(Addr pc,
240 const SymbolTable *symtab) const
242 std::stringstream response;
243 bool load = flags[IsLoad];
244 bool save = flags[IsStore];
246 printMnemonic(response, mnemonic);
249 printReg(response, _srcRegIdx[1]);
250 ccprintf(response, ", ");
252 ccprintf(response, "[ ");
253 printReg(response, _srcRegIdx[0]);
255 ccprintf(response, " + 0x%x ]", imm);
257 ccprintf(response, " + -0x%x ]", -imm);
260 ccprintf(response, ", ");
261 printReg(response, _destRegIdx[0]);
264 return response.str();
269 def template BlockMemDeclare {{
271 * Static instruction class for a block memory operation
273 class %(class_name)s : public %(base_class)s
277 %(class_name)s(ExtMachInst machInst);
280 class %(class_name)s_0 : public %(base_class)sMicro
284 %(class_name)s_0(ExtMachInst machInst);
286 %(InitiateAccDeclare)s
287 %(CompleteAccDeclare)s
290 class %(class_name)s_1 : public %(base_class)sMicro
294 %(class_name)s_1(ExtMachInst machInst);
296 %(InitiateAccDeclare)s
297 %(CompleteAccDeclare)s
300 class %(class_name)s_2 : public %(base_class)sMicro
304 %(class_name)s_2(ExtMachInst machInst);
306 %(InitiateAccDeclare)s
307 %(CompleteAccDeclare)s
310 class %(class_name)s_3 : public %(base_class)sMicro
314 %(class_name)s_3(ExtMachInst machInst);
316 %(InitiateAccDeclare)s
317 %(CompleteAccDeclare)s
320 class %(class_name)s_4 : public %(base_class)sMicro
324 %(class_name)s_4(ExtMachInst machInst);
326 %(InitiateAccDeclare)s
327 %(CompleteAccDeclare)s
330 class %(class_name)s_5 : public %(base_class)sMicro
334 %(class_name)s_5(ExtMachInst machInst);
336 %(InitiateAccDeclare)s
337 %(CompleteAccDeclare)s
340 class %(class_name)s_6 : public %(base_class)sMicro
344 %(class_name)s_6(ExtMachInst machInst);
346 %(InitiateAccDeclare)s
347 %(CompleteAccDeclare)s
350 class %(class_name)s_7 : public %(base_class)sMicro
354 %(class_name)s_7(ExtMachInst machInst);
356 %(InitiateAccDeclare)s
357 %(CompleteAccDeclare)s
362 def template TwinMemDeclare {{
364 * Static instruction class for a block memory operation
366 class %(class_name)s : public %(base_class)s
370 %(class_name)s(ExtMachInst machInst);
373 class %(class_name)s_0 : public %(base_class)sMicro
377 %(class_name)s_0(ExtMachInst machInst);
379 %(InitiateAccDeclare)s
380 %(CompleteAccDeclare)s
383 class %(class_name)s_1 : public %(base_class)sMicro
387 %(class_name)s_1(ExtMachInst machInst);
389 %(InitiateAccDeclare)s
390 %(CompleteAccDeclare)s
395 // Basic instruction class constructor template.
396 def template BlockMemConstructor {{
397 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
398 : %(base_class)s("%(mnemonic)s", machInst)
401 microOps[0] = new %(class_name)s_0(machInst);
402 microOps[1] = new %(class_name)s_1(machInst);
403 microOps[2] = new %(class_name)s_2(machInst);
404 microOps[3] = new %(class_name)s_3(machInst);
405 microOps[4] = new %(class_name)s_4(machInst);
406 microOps[5] = new %(class_name)s_5(machInst);
407 microOps[6] = new %(class_name)s_6(machInst);
408 microOps[7] = new %(class_name)s_7(machInst);
412 // Basic instruction class constructor template.
413 def template TwinMemConstructor {{
414 inline %(class_name)s::%(class_name)s(ExtMachInst machInst)
415 : %(base_class)s("%(mnemonic)s", machInst)
418 microOps[0] = new %(class_name)s_0(machInst);
419 microOps[1] = new %(class_name)s_1(machInst);
423 def template BlockMemMicroConstructor {{
424 inline %(class_name)s::
425 %(class_name)s_%(micro_pc)s::
426 %(class_name)s_%(micro_pc)s(ExtMachInst machInst) :
427 %(base_class)sMicro("%(mnemonic)s[%(micro_pc)s]",
428 machInst, %(op_class)s, %(micro_pc)s * 8)
437 def doBlockMemFormat(code, faultCode, execute, name, Name, asi, opt_flags):
438 # XXX Need to take care of pstate.hpriv as well. The lower ASIs
439 # are split into ones that are available in priv and hpriv, and
440 # those that are only available in hpriv
441 addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
442 addrCalcImm = 'EA = Rs1 + imm + offset;'
443 iop = InstObjParams(name, Name, 'BlockMem', code, opt_flags)
444 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm', code, opt_flags)
445 header_output = BlockMemDeclare.subst(iop) + BlockMemDeclare.subst(iop_imm)
446 decoder_output = BlockMemConstructor.subst(iop) + BlockMemConstructor.subst(iop_imm)
447 decode_block = ROrImmDecode.subst(iop)
448 matcher = re.compile(r'Frd_N')
450 for microPc in range(8):
453 flag_code = "flags[IsLastMicroOp] = true;"
455 flag_code = "flags[IsDelayedCommit] = true;"
456 pcedCode = matcher.sub("Frd_%d" % microPc, code)
457 iop = InstObjParams(name, Name, 'BlockMem',
458 {"code": pcedCode, "ea_code": addrCalcReg,
459 "fault_check": faultCode, "micro_pc": microPc,
460 "set_flags": flag_code}, opt_flags)
461 iop_imm = InstObjParams(name, Name + 'Imm', 'BlockMemImm',
462 {"code": pcedCode, "ea_code": addrCalcImm,
463 "fault_check": faultCode, "micro_pc": microPc,
464 "set_flags": flag_code}, opt_flags)
465 decoder_output += BlockMemMicroConstructor.subst(iop)
466 decoder_output += BlockMemMicroConstructor.subst(iop_imm)
467 exec_output += doDualSplitExecute(
468 pcedCode, addrCalcReg, addrCalcImm, execute, faultCode,
469 makeMicroName(name, microPc),
470 makeMicroName(name + "Imm", microPc),
471 makeMicroName(Name, microPc),
472 makeMicroName(Name + "Imm", microPc),
475 return (header_output, decoder_output, exec_output, decode_block)
478 def doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags):
479 addrCalcReg = 'EA = Rs1 + Rs2 + offset;'
480 addrCalcImm = 'EA = Rs1 + imm + offset;'
481 iop = InstObjParams(name, Name, 'TwinMem', code, opt_flags)
482 iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm', code, opt_flags)
483 header_output = TwinMemDeclare.subst(iop) + TwinMemDeclare.subst(iop_imm)
484 decoder_output = TwinMemConstructor.subst(iop) + TwinMemConstructor.subst(iop_imm)
485 decode_block = ROrImmDecode.subst(iop)
486 matcher = re.compile(r'RdTwin')
488 for microPc in range(2):
492 flag_code = "flags[IsLastMicroOp] = true;"
493 pcedCode = matcher.sub("RdHigh", code)
495 flag_code = "flags[IsDelayedCommit] = true;"
496 pcedCode = matcher.sub("RdLow", code)
497 iop = InstObjParams(name, Name, 'TwinMem',
498 {"code": pcedCode, "ea_code": addrCalcReg,
499 "fault_check": faultCode, "micro_pc": microPc,
500 "set_flags": flag_code}, opt_flags)
501 iop_imm = InstObjParams(name, Name + 'Imm', 'TwinMemImm',
502 {"code": pcedCode, "ea_code": addrCalcImm,
503 "fault_check": faultCode, "micro_pc": microPc,
504 "set_flags": flag_code}, opt_flags)
505 decoder_output += BlockMemMicroConstructor.subst(iop)
506 decoder_output += BlockMemMicroConstructor.subst(iop_imm)
507 exec_output += doDualSplitExecute(
508 pcedCode, addrCalcReg, addrCalcImm, LoadFuncs, faultCode,
509 makeMicroName(name, microPc),
510 makeMicroName(name + "Imm", microPc),
511 makeMicroName(Name, microPc),
512 makeMicroName(Name + "Imm", microPc),
515 return (header_output, decoder_output, exec_output, decode_block)
519 def format BlockLoad(code, asi, *opt_flags) {{
520 # We need to make sure to check the highest priority fault last.
521 # That way, if other faults have been detected, they'll be overwritten
522 # rather than the other way around.
523 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
527 decode_block) = doBlockMemFormat(code, faultCode,
528 LoadFuncs, name, Name, asi, opt_flags)
531 def format BlockStore(code, asi, *opt_flags) {{
532 # We need to make sure to check the highest priority fault last.
533 # That way, if other faults have been detected, they'll be overwritten
534 # rather than the other way around.
535 faultCode = AlternateASIPrivFaultCheck + BlockAlignmentFaultCheck
539 decode_block) = doBlockMemFormat(code, faultCode,
540 StoreFuncs, name, Name, asi, opt_flags)
543 def format TwinLoad(code, asi, *opt_flags) {{
544 faultCode = AlternateASIPrivFaultCheck + TwinAlignmentFaultCheck
548 decode_block) = doTwinLoadFormat(code, faultCode, name, Name, asi, opt_flags)