b71542a2bafca8050608eb5ff9f37e42c3ebd337
[gem5.git] / src / arch / sparc / isa / formats / mem / swap.isa
1 // Copyright (c) 2007 The Regents of The University of Michigan
2 // All rights reserved.
3 //
4 // Redistribution and use in source and binary forms, with or without
5 // modification, are permitted provided that the following conditions are
6 // met: redistributions of source code must retain the above copyright
7 // notice, this list of conditions and the following disclaimer;
8 // redistributions in binary form must reproduce the above copyright
9 // notice, this list of conditions and the following disclaimer in the
10 // documentation and/or other materials provided with the distribution;
11 // neither the name of the copyright holders nor the names of its
12 // contributors may be used to endorse or promote products derived from
13 // this software without specific prior written permission.
14 //
15 // THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
16 // "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
17 // LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
18 // A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
19 // OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
20 // SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
21 // LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
22 // DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
23 // THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
24 // (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
25 // OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
26 //
27 // Authors: Gabe Black
28 // Ali Saidi
29
30 //This template provides the execute functions for a swap
31 def template SwapExecute {{
32 Fault %(class_name)s::execute(%(CPU_exec_context)s *xc,
33 Trace::InstRecord *traceData) const
34 {
35 Fault fault = NoFault;
36 //This is to support the conditional store in cas instructions.
37 //It should be optomized out in all the others
38 bool storeCond = true;
39 Addr EA;
40 %(fp_enable_check)s;
41 %(op_decl)s;
42 uint64_t mem_data;
43
44 %(op_rd)s;
45 %(ea_code)s;
46 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
47 %(fault_check)s;
48 if(fault == NoFault)
49 {
50 %(code)s;
51 }
52 if(storeCond && fault == NoFault)
53 {
54 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
55 EA, %(asi_val)s, &mem_data);
56 }
57 if(fault == NoFault)
58 {
59 //Handle the swapping
60 %(postacc_code)s;
61 }
62 if(fault == NoFault)
63 {
64 //Write the resulting state to the execution context
65 %(op_wb)s;
66 }
67
68 return fault;
69 }
70 }};
71
72
73 def template SwapInitiateAcc {{
74 Fault %(class_name)s::initiateAcc(%(CPU_exec_context)s * xc,
75 Trace::InstRecord * traceData) const
76 {
77 Fault fault = NoFault;
78 Addr EA;
79 %(fp_enable_check)s;
80 uint64_t mem_data = 0;
81 %(op_decl)s;
82 %(op_rd)s;
83 %(ea_code)s;
84
85 DPRINTF(Sparc, "%s: The address is 0x%x\n", mnemonic, EA);
86 %(fault_check)s;
87
88 if(fault == NoFault)
89 {
90 %(code)s;
91 }
92 if(fault == NoFault)
93 {
94 fault = xc->write((uint%(mem_acc_size)s_t)Mem,
95 EA, %(asi_val)s, &mem_data);
96 }
97 return fault;
98 }
99 }};
100
101
102
103 def template SwapCompleteAcc {{
104 Fault %(class_name)s::completeAcc(PacketPtr pkt, %(CPU_exec_context)s * xc,
105 Trace::InstRecord * traceData) const
106 {
107 Fault fault = NoFault;
108 %(op_decl)s;
109
110 uint64_t mem_data = pkt->get<uint%(mem_acc_size)s_t>();
111
112 if(fault == NoFault)
113 {
114 //Handle the swapping
115 %(postacc_code)s;
116 }
117 if(fault == NoFault)
118 {
119 //Write the resulting state to the execution context
120 %(op_wb)s;
121 }
122
123 return fault;
124 }
125 }};
126
127 let {{
128 SwapFuncs = [SwapExecute, SwapInitiateAcc, SwapCompleteAcc]
129 }};
130
131
132 def format Swap(code, postacc_code, mem_flags, *opt_flags) {{
133 mem_flags = makeList(mem_flags)
134 flags = string.join(mem_flags, '|')
135
136 (header_output,
137 decoder_output,
138 exec_output,
139 decode_block) = doMemFormat(code, SwapFuncs, '', name, Name, flags,
140 ["IsStoreConditional"], postacc_code)
141 }};
142
143 def format SwapAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
144 mem_flags = makeList(mem_flags)
145 mem_flags.append(asi)
146 flags = string.join(mem_flags, '|')
147 (header_output,
148 decoder_output,
149 exec_output,
150 decode_block) = doMemFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
151 name, Name, flags, ["IsStoreConditional"], postacc_code)
152 }};
153
154
155 let {{
156 def doCasFormat(code, execute, faultCode, name, Name, asi, opt_flags, postacc_code = ''):
157 addrCalcReg = 'EA = Rs1;'
158 iop = InstObjParams(name, Name, 'Mem',
159 {"code": code, "postacc_code" : postacc_code,
160 "fault_check": faultCode, "ea_code": addrCalcReg}, opt_flags)
161 header_output = MemDeclare.subst(iop)
162 decoder_output = BasicConstructor.subst(iop)
163 decode_block = BasicDecode.subst(iop)
164 microParams = {"code": code, "postacc_code" : postacc_code,
165 "ea_code" : addrCalcReg, "fault_check" : faultCode}
166 exec_output = doSplitExecute(execute, name, Name, asi,
167 ["IsStoreConditional"], microParams);
168 return (header_output, decoder_output, exec_output, decode_block)
169 }};
170
171
172 def format CasAlt(code, postacc_code, asi, mem_flags, *opt_flags) {{
173 mem_flags = makeList(mem_flags)
174 mem_flags.append(asi)
175 flags = string.join(mem_flags, '|')
176 (header_output,
177 decoder_output,
178 exec_output,
179 decode_block) = doCasFormat(code, SwapFuncs, AlternateASIPrivFaultCheck,
180 name, Name, flags, ["IsStoreConditional"], postacc_code)
181 }};
182
183