2 * Copyright (c) 2009 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
31 #include "arch/sparc/asi.hh"
32 #include "arch/sparc/isa.hh"
33 #include "base/bitfield.hh"
34 #include "base/trace.hh"
35 #include "config/full_system.hh"
36 #include "cpu/base.hh"
37 #include "cpu/thread_context.hh"
38 #include "debug/MiscRegs.hh"
39 #include "debug/Timer.hh"
46 PSTATE_MASK
= (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
52 installGlobals(gl
, CurrentGlobalsOffset
);
53 installWindow(cwp
, CurrentWindowOffset
);
54 // Microcode registers.
55 for (int i
= 0; i
< NumMicroIntRegs
; i
++)
56 intRegMap
[MicroIntOffset
+ i
] = i
+ TotalGlobals
+ NWindows
* 16;
57 installGlobals(gl
, NextGlobalsOffset
);
58 installWindow(cwp
- 1, NextWindowOffset
);
59 installGlobals(gl
, PreviousGlobalsOffset
);
60 installWindow(cwp
+ 1, PreviousWindowOffset
);
64 ISA::installWindow(int cwp
, int offset
)
66 assert(offset
>= 0 && offset
+ NumWindowedRegs
<= NumIntRegs
);
67 RegIndex
*mapChunk
= intRegMap
+ offset
;
68 for (int i
= 0; i
< NumWindowedRegs
; i
++)
69 mapChunk
[i
] = TotalGlobals
+
70 ((i
- cwp
* RegsPerWindow
+ TotalWindowed
) % (TotalWindowed
));
74 ISA::installGlobals(int gl
, int offset
)
76 assert(offset
>= 0 && offset
+ NumGlobalRegs
<= NumIntRegs
);
77 RegIndex
*mapChunk
= intRegMap
+ offset
;
79 for (int i
= 1; i
< NumGlobalRegs
; i
++)
80 mapChunk
[i
] = i
+ gl
* NumGlobalRegs
;
100 memset(tpc
, 0, sizeof(tpc
));
101 memset(tnpc
, 0, sizeof(tnpc
));
102 memset(tstate
, 0, sizeof(tstate
));
103 memset(tt
, 0, sizeof(tt
));
113 // In a T1, bit 11 is apparently always 1
115 memset(htstate
, 0, sizeof(htstate
));
119 // This is set this way in Legion for some reason
120 strandStatusReg
= 0x50000;
128 memset(scratchPad
, 0, sizeof(scratchPad
));
140 // If one of these events is active, it's not obvious to me how to get
141 // rid of it cleanly. For now we'll just assert that they're not.
142 if (tickCompare
!= NULL
&& sTickCompare
!= NULL
&& hSTickCompare
!= NULL
)
143 panic("Tick comparison event active when clearing the ISA object.\n");
148 ISA::readMiscRegNoEffect(int miscReg
)
151 // The three miscRegs are moved up from the switch statement
152 // due to more frequent calls.
154 if (miscReg
== MISCREG_GL
)
156 if (miscReg
== MISCREG_CWP
)
158 if (miscReg
== MISCREG_TLB_DATA
) {
159 /* Package up all the data for the tlb:
160 * 6666555555555544444444443333333333222222222211111111110000000000
161 * 3210987654321098765432109876543210987654321098765432109876543210
162 * secContext | priContext | |tl|partid| |||||^hpriv
169 return bits((uint64_t)hpstate
,2,2) |
170 bits((uint64_t)hpstate
,5,5) << 1 |
171 bits((uint64_t)pstate
,3,2) << 2 |
172 bits((uint64_t)lsuCtrlReg
,3,2) << 4 |
173 bits((uint64_t)partId
,7,0) << 8 |
174 bits((uint64_t)tl
,2,0) << 16 |
175 (uint64_t)priContext
<< 32 |
176 (uint64_t)secContext
<< 48;
180 // case MISCREG_TLB_DATA:
181 // [original contents see above]
193 panic("PCR not implemented\n");
195 panic("PIC not implemented\n");
198 case MISCREG_SOFTINT
:
200 case MISCREG_TICK_CMPR
:
204 case MISCREG_STICK_CMPR
:
207 /** Privilged Registers */
216 case MISCREG_PRIVTICK
:
217 panic("Priviliged access to tick registers not implemented\n");
229 // case MISCREG_CANSAVE:
231 // case MISCREG_CANRESTORE:
232 // return canrestore;
233 // case MISCREG_CLEANWIN:
235 // case MISCREG_OTHERWIN:
237 // case MISCREG_WSTATE:
242 /** Hyper privileged registers */
243 case MISCREG_HPSTATE
:
245 case MISCREG_HTSTATE
:
246 return htstate
[tl
-1];
251 case MISCREG_STRAND_STS_REG
:
252 return strandStatusReg
;
253 case MISCREG_HSTICK_CMPR
:
256 /** Floating Point Status Register */
258 DPRINTF(MiscRegs
, "FSR read as: %#x\n", fsr
);
261 case MISCREG_MMU_P_CONTEXT
:
263 case MISCREG_MMU_S_CONTEXT
:
265 case MISCREG_MMU_PART_ID
:
267 case MISCREG_MMU_LSU_CTRL
:
270 case MISCREG_SCRATCHPAD_R0
:
271 return scratchPad
[0];
272 case MISCREG_SCRATCHPAD_R1
:
273 return scratchPad
[1];
274 case MISCREG_SCRATCHPAD_R2
:
275 return scratchPad
[2];
276 case MISCREG_SCRATCHPAD_R3
:
277 return scratchPad
[3];
278 case MISCREG_SCRATCHPAD_R4
:
279 return scratchPad
[4];
280 case MISCREG_SCRATCHPAD_R5
:
281 return scratchPad
[5];
282 case MISCREG_SCRATCHPAD_R6
:
283 return scratchPad
[6];
284 case MISCREG_SCRATCHPAD_R7
:
285 return scratchPad
[7];
286 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
287 return cpu_mondo_head
;
288 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
289 return cpu_mondo_tail
;
290 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
291 return dev_mondo_head
;
292 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
293 return dev_mondo_tail
;
294 case MISCREG_QUEUE_RES_ERROR_HEAD
:
295 return res_error_head
;
296 case MISCREG_QUEUE_RES_ERROR_TAIL
:
297 return res_error_tail
;
298 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
299 return nres_error_head
;
300 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
301 return nres_error_tail
;
303 panic("Miscellaneous register %d not implemented\n", miscReg
);
308 ISA::readMiscReg(int miscReg
, ThreadContext
* tc
)
311 // tick and stick are aliased to each other in niagra
312 // well store the tick data in stick and the interrupt bit in tick
315 case MISCREG_PRIVTICK
:
316 // I'm not sure why legion ignores the lowest two bits, but we'll go
318 // change from curCycle() to instCount() until we're done with legion
319 DPRINTF(Timer
, "Instruction Count when TICK read: %#X stick=%#X\n",
320 tc
->getCpuPtr()->instCount(), stick
);
321 return mbits(tc
->getCpuPtr()->instCount() + (int64_t)stick
,62,2) |
324 // in legion if fp is enabled du and dl are set
328 panic("Performance Instrumentation not impl\n");
329 case MISCREG_SOFTINT_CLR
:
330 case MISCREG_SOFTINT_SET
:
331 panic("Can read from softint clr/set\n");
332 case MISCREG_SOFTINT
:
333 case MISCREG_TICK_CMPR
:
334 case MISCREG_STICK_CMPR
:
336 case MISCREG_HTSTATE
:
339 case MISCREG_STRAND_STS_REG
:
340 case MISCREG_HSTICK_CMPR
:
341 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
342 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
343 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
344 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
345 case MISCREG_QUEUE_RES_ERROR_HEAD
:
346 case MISCREG_QUEUE_RES_ERROR_TAIL
:
347 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
348 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
350 case MISCREG_HPSTATE
:
351 return readFSReg(miscReg
, tc
);
353 case MISCREG_HPSTATE
:
354 // HPSTATE is special because because sometimes in privilege
355 // checks for instructions it will read HPSTATE to make sure
356 // the priv. level is ok So, we'll just have to tell it it
357 // isn't, instead of panicing.
360 panic("Accessing Fullsystem register %d in SE mode\n", miscReg
);
364 return readMiscRegNoEffect(miscReg
);
368 ISA::setMiscRegNoEffect(int miscReg
, MiscReg val
)
387 panic("PCR not implemented\n");
389 panic("PIC not implemented\n");
393 case MISCREG_SOFTINT
:
396 case MISCREG_TICK_CMPR
:
402 case MISCREG_STICK_CMPR
:
406 /** Privilged Registers */
419 case MISCREG_PRIVTICK
:
420 panic("Priviliged access to tick regesiters not implemented\n");
422 // clear lower 7 bits on writes.
423 tba
= val
& ULL(~0x7FFF);
426 pstate
= (val
& PSTATE_MASK
);
437 // case MISCREG_CANSAVE:
440 // case MISCREG_CANRESTORE:
443 // case MISCREG_CLEANWIN:
446 // case MISCREG_OTHERWIN:
449 // case MISCREG_WSTATE:
456 /** Hyper privileged registers */
457 case MISCREG_HPSTATE
:
460 case MISCREG_HTSTATE
:
468 case MISCREG_STRAND_STS_REG
:
469 strandStatusReg
= val
;
471 case MISCREG_HSTICK_CMPR
:
475 /** Floating Point Status Register */
478 DPRINTF(MiscRegs
, "FSR written with: %#x\n", fsr
);
481 case MISCREG_MMU_P_CONTEXT
:
484 case MISCREG_MMU_S_CONTEXT
:
487 case MISCREG_MMU_PART_ID
:
490 case MISCREG_MMU_LSU_CTRL
:
494 case MISCREG_SCRATCHPAD_R0
:
497 case MISCREG_SCRATCHPAD_R1
:
500 case MISCREG_SCRATCHPAD_R2
:
503 case MISCREG_SCRATCHPAD_R3
:
506 case MISCREG_SCRATCHPAD_R4
:
509 case MISCREG_SCRATCHPAD_R5
:
512 case MISCREG_SCRATCHPAD_R6
:
515 case MISCREG_SCRATCHPAD_R7
:
518 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
519 cpu_mondo_head
= val
;
521 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
522 cpu_mondo_tail
= val
;
524 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
525 dev_mondo_head
= val
;
527 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
528 dev_mondo_tail
= val
;
530 case MISCREG_QUEUE_RES_ERROR_HEAD
:
531 res_error_head
= val
;
533 case MISCREG_QUEUE_RES_ERROR_TAIL
:
534 res_error_tail
= val
;
536 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
537 nres_error_head
= val
;
539 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
540 nres_error_tail
= val
;
543 panic("Miscellaneous register %d not implemented\n", miscReg
);
548 ISA::setMiscReg(int miscReg
, MiscReg val
, ThreadContext
* tc
)
550 MiscReg new_val
= val
;
555 // stick and tick are same thing on niagra
556 // use stick for offset and tick for holding intrrupt bit
557 stick
= mbits(val
,62,0) - tc
->getCpuPtr()->instCount();
558 tick
= mbits(val
,63,63);
559 DPRINTF(Timer
, "Writing TICK=%#X\n", val
);
562 // Configure the fpu based on the fprs
565 // Set up performance counting based on pcr value
568 pstate
= val
& PSTATE_MASK
;
573 if (hpstate
& HPSTATE::tlz
&& tl
== 0 && !(hpstate
& HPSTATE::hpriv
))
574 tc
->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
576 tc
->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO
, 0);
580 new_val
= val
>= NWindows
? NWindows
- 1 : val
;
582 new_val
= NWindows
- 1;
584 installWindow(new_val
, CurrentWindowOffset
);
585 installWindow(new_val
- 1, NextWindowOffset
);
586 installWindow(new_val
+ 1, PreviousWindowOffset
);
589 installGlobals(val
, CurrentGlobalsOffset
);
590 installGlobals(val
, NextGlobalsOffset
);
591 installGlobals(val
, PreviousGlobalsOffset
);
594 case MISCREG_SOFTINT
:
595 case MISCREG_SOFTINT_SET
:
596 case MISCREG_SOFTINT_CLR
:
597 case MISCREG_TICK_CMPR
:
598 case MISCREG_STICK_CMPR
:
600 case MISCREG_HTSTATE
:
603 case MISCREG_STRAND_STS_REG
:
604 case MISCREG_HSTICK_CMPR
:
605 case MISCREG_QUEUE_CPU_MONDO_HEAD
:
606 case MISCREG_QUEUE_CPU_MONDO_TAIL
:
607 case MISCREG_QUEUE_DEV_MONDO_HEAD
:
608 case MISCREG_QUEUE_DEV_MONDO_TAIL
:
609 case MISCREG_QUEUE_RES_ERROR_HEAD
:
610 case MISCREG_QUEUE_RES_ERROR_TAIL
:
611 case MISCREG_QUEUE_NRES_ERROR_HEAD
:
612 case MISCREG_QUEUE_NRES_ERROR_TAIL
:
614 case MISCREG_HPSTATE
:
615 setFSReg(miscReg
, val
, tc
);
618 case MISCREG_HPSTATE
:
619 // HPSTATE is special because normal trap processing saves HPSTATE when
620 // it goes into a trap, and restores it when it returns.
622 panic("Accessing Fullsystem register %d to %#x in SE mode\n",
626 setMiscRegNoEffect(miscReg
, new_val
);
630 ISA::serialize(EventManager
*em
, std::ostream
&os
)
632 SERIALIZE_SCALAR(asi
);
633 SERIALIZE_SCALAR(tick
);
634 SERIALIZE_SCALAR(fprs
);
635 SERIALIZE_SCALAR(gsr
);
636 SERIALIZE_SCALAR(softint
);
637 SERIALIZE_SCALAR(tick_cmpr
);
638 SERIALIZE_SCALAR(stick
);
639 SERIALIZE_SCALAR(stick_cmpr
);
640 SERIALIZE_ARRAY(tpc
,MaxTL
);
641 SERIALIZE_ARRAY(tnpc
,MaxTL
);
642 SERIALIZE_ARRAY(tstate
,MaxTL
);
643 SERIALIZE_ARRAY(tt
,MaxTL
);
644 SERIALIZE_SCALAR(tba
);
645 SERIALIZE_SCALAR(pstate
);
646 SERIALIZE_SCALAR(tl
);
647 SERIALIZE_SCALAR(pil
);
648 SERIALIZE_SCALAR(cwp
);
649 SERIALIZE_SCALAR(gl
);
650 SERIALIZE_SCALAR(hpstate
);
651 SERIALIZE_ARRAY(htstate
,MaxTL
);
652 SERIALIZE_SCALAR(hintp
);
653 SERIALIZE_SCALAR(htba
);
654 SERIALIZE_SCALAR(hstick_cmpr
);
655 SERIALIZE_SCALAR(strandStatusReg
);
656 SERIALIZE_SCALAR(fsr
);
657 SERIALIZE_SCALAR(priContext
);
658 SERIALIZE_SCALAR(secContext
);
659 SERIALIZE_SCALAR(partId
);
660 SERIALIZE_SCALAR(lsuCtrlReg
);
661 SERIALIZE_ARRAY(scratchPad
,8);
662 SERIALIZE_SCALAR(cpu_mondo_head
);
663 SERIALIZE_SCALAR(cpu_mondo_tail
);
664 SERIALIZE_SCALAR(dev_mondo_head
);
665 SERIALIZE_SCALAR(dev_mondo_tail
);
666 SERIALIZE_SCALAR(res_error_head
);
667 SERIALIZE_SCALAR(res_error_tail
);
668 SERIALIZE_SCALAR(nres_error_head
);
669 SERIALIZE_SCALAR(nres_error_tail
);
671 Tick tick_cmp
= 0, stick_cmp
= 0, hstick_cmp
= 0;
672 ThreadContext
*tc
= NULL
;
675 bool tick_intr_sched
= true;
678 tc
= tickCompare
->getTC();
679 else if (sTickCompare
)
680 tc
= sTickCompare
->getTC();
681 else if (hSTickCompare
)
682 tc
= hSTickCompare
->getTC();
684 tick_intr_sched
= false;
686 SERIALIZE_SCALAR(tick_intr_sched
);
689 cpu
= tc
->getCpuPtr();
690 tc_num
= cpu
->findContext(tc
);
691 if (tickCompare
&& tickCompare
->scheduled())
692 tick_cmp
= tickCompare
->when();
693 if (sTickCompare
&& sTickCompare
->scheduled())
694 stick_cmp
= sTickCompare
->when();
695 if (hSTickCompare
&& hSTickCompare
->scheduled())
696 hstick_cmp
= hSTickCompare
->when();
698 SERIALIZE_OBJPTR(cpu
);
699 SERIALIZE_SCALAR(tc_num
);
700 SERIALIZE_SCALAR(tick_cmp
);
701 SERIALIZE_SCALAR(stick_cmp
);
702 SERIALIZE_SCALAR(hstick_cmp
);
708 ISA::unserialize(EventManager
*em
, Checkpoint
*cp
, const std::string
§ion
)
710 UNSERIALIZE_SCALAR(asi
);
711 UNSERIALIZE_SCALAR(tick
);
712 UNSERIALIZE_SCALAR(fprs
);
713 UNSERIALIZE_SCALAR(gsr
);
714 UNSERIALIZE_SCALAR(softint
);
715 UNSERIALIZE_SCALAR(tick_cmpr
);
716 UNSERIALIZE_SCALAR(stick
);
717 UNSERIALIZE_SCALAR(stick_cmpr
);
718 UNSERIALIZE_ARRAY(tpc
,MaxTL
);
719 UNSERIALIZE_ARRAY(tnpc
,MaxTL
);
720 UNSERIALIZE_ARRAY(tstate
,MaxTL
);
721 UNSERIALIZE_ARRAY(tt
,MaxTL
);
722 UNSERIALIZE_SCALAR(tba
);
723 UNSERIALIZE_SCALAR(pstate
);
724 UNSERIALIZE_SCALAR(tl
);
725 UNSERIALIZE_SCALAR(pil
);
726 UNSERIALIZE_SCALAR(cwp
);
727 UNSERIALIZE_SCALAR(gl
);
729 UNSERIALIZE_SCALAR(hpstate
);
730 UNSERIALIZE_ARRAY(htstate
,MaxTL
);
731 UNSERIALIZE_SCALAR(hintp
);
732 UNSERIALIZE_SCALAR(htba
);
733 UNSERIALIZE_SCALAR(hstick_cmpr
);
734 UNSERIALIZE_SCALAR(strandStatusReg
);
735 UNSERIALIZE_SCALAR(fsr
);
736 UNSERIALIZE_SCALAR(priContext
);
737 UNSERIALIZE_SCALAR(secContext
);
738 UNSERIALIZE_SCALAR(partId
);
739 UNSERIALIZE_SCALAR(lsuCtrlReg
);
740 UNSERIALIZE_ARRAY(scratchPad
,8);
741 UNSERIALIZE_SCALAR(cpu_mondo_head
);
742 UNSERIALIZE_SCALAR(cpu_mondo_tail
);
743 UNSERIALIZE_SCALAR(dev_mondo_head
);
744 UNSERIALIZE_SCALAR(dev_mondo_tail
);
745 UNSERIALIZE_SCALAR(res_error_head
);
746 UNSERIALIZE_SCALAR(res_error_tail
);
747 UNSERIALIZE_SCALAR(nres_error_head
);
748 UNSERIALIZE_SCALAR(nres_error_tail
);
751 Tick tick_cmp
= 0, stick_cmp
= 0, hstick_cmp
= 0;
752 ThreadContext
*tc
= NULL
;
755 bool tick_intr_sched
;
756 UNSERIALIZE_SCALAR(tick_intr_sched
);
757 if (tick_intr_sched
) {
758 UNSERIALIZE_OBJPTR(cpu
);
760 UNSERIALIZE_SCALAR(tc_num
);
761 UNSERIALIZE_SCALAR(tick_cmp
);
762 UNSERIALIZE_SCALAR(stick_cmp
);
763 UNSERIALIZE_SCALAR(hstick_cmp
);
764 tc
= cpu
->getContext(tc_num
);
767 tickCompare
= new TickCompareEvent(this, tc
);
768 em
->schedule(tickCompare
, tick_cmp
);
771 sTickCompare
= new STickCompareEvent(this, tc
);
772 em
->schedule(sTickCompare
, stick_cmp
);
775 hSTickCompare
= new HSTickCompareEvent(this, tc
);
776 em
->schedule(hSTickCompare
, hstick_cmp
);