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31 #ifndef __ARCH_SPARC_ISA_HH__
32 #define __ARCH_SPARC_ISA_HH__
37 #include "arch/sparc/registers.hh"
38 #include "arch/sparc/types.hh"
39 #include "cpu/cpuevent.hh"
52 // uint64_t y; // Y (used in obsolete multiplication)
53 // uint8_t ccr; // Condition Code Register
54 uint8_t asi; // Address Space Identifier
55 uint64_t tick; // Hardware clock-tick counter
56 uint8_t fprs; // Floating-Point Register State
57 uint64_t gsr; // General Status Register
59 uint64_t tick_cmpr; // Hardware tick compare registers
60 uint64_t stick; // Hardware clock-tick counter
61 uint64_t stick_cmpr; // Hardware tick compare registers
64 /* Privileged Registers */
65 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
66 // previous trap level)
67 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
68 // previous trap level)
69 uint64_t tstate[MaxTL]; // Trap State
70 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
71 // on the previous level)
72 uint64_t tba; // Trap Base Address
74 PSTATE pstate; // Process State Register
75 uint8_t tl; // Trap Level
76 uint8_t pil; // Process Interrupt Register
77 uint8_t cwp; // Current Window Pointer
78 // uint8_t cansave; // Savable windows
79 // uint8_t canrestore; // Restorable windows
80 // uint8_t cleanwin; // Clean windows
81 // uint8_t otherwin; // Other windows
82 // uint8_t wstate; // Window State
83 uint8_t gl; // Global level register
85 /** Hyperprivileged Registers */
86 HPSTATE hpstate; // Hyperprivileged State Register
87 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
89 uint64_t htba; // Hyperprivileged Trap Base Address register
90 uint64_t hstick_cmpr; // Hardware tick compare registers
92 uint64_t strandStatusReg;// Per strand status register
94 /** Floating point misc registers. */
95 uint64_t fsr; // Floating-Point State Register
97 /** MMU Internal Registers */
103 uint64_t scratchPad[8];
105 uint64_t cpu_mondo_head;
106 uint64_t cpu_mondo_tail;
107 uint64_t dev_mondo_head;
108 uint64_t dev_mondo_tail;
109 uint64_t res_error_head;
110 uint64_t res_error_tail;
111 uint64_t nres_error_head;
112 uint64_t nres_error_tail;
114 // These need to check the int_dis field and if 0 then
115 // set appropriate bit in softint and checkinterrutps on the cpu
116 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
117 MiscReg readFSReg(int miscReg, ThreadContext * tc);
119 // Update interrupt state on softint or pil change
120 void checkSoftInt(ThreadContext *tc);
122 /** Process a tick compare event and generate an interrupt on the cpu if
124 void processTickCompare(ThreadContext *tc);
125 void processSTickCompare(ThreadContext *tc);
126 void processHSTickCompare(ThreadContext *tc);
128 typedef CpuEventWrapper<ISA,
129 &ISA::processTickCompare> TickCompareEvent;
130 TickCompareEvent *tickCompare;
132 typedef CpuEventWrapper<ISA,
133 &ISA::processSTickCompare> STickCompareEvent;
134 STickCompareEvent *sTickCompare;
136 typedef CpuEventWrapper<ISA,
137 &ISA::processHSTickCompare> HSTickCompareEvent;
138 HSTickCompareEvent *hSTickCompare;
140 static const int NumGlobalRegs = 8;
141 static const int NumWindowedRegs = 24;
142 static const int WindowOverlap = 8;
144 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
145 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
146 static const int TotalWindowed = NWindows * RegsPerWindow;
148 enum InstIntRegOffsets {
149 CurrentGlobalsOffset = 0,
150 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
151 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
152 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
153 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
154 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
155 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
156 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
159 RegIndex intRegMap[TotalInstIntRegs];
160 void installWindow(int cwp, int offset);
161 void installGlobals(int gl, int offset);
168 void serialize(EventManager *em, std::ostream & os);
170 void unserialize(EventManager *em, Checkpoint *cp,
171 const std::string & section);
175 bool isHyperPriv() { return hpstate.hpriv; }
176 bool isPriv() { return hpstate.hpriv || pstate.priv; }
177 bool isNonPriv() { return !isPriv(); }
181 MiscReg readMiscRegNoEffect(int miscReg);
182 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
184 void setMiscRegNoEffect(int miscReg, const MiscReg val);
185 void setMiscReg(int miscReg, const MiscReg val,
189 flattenIntIndex(int reg)
191 assert(reg < TotalInstIntRegs);
192 RegIndex flatIndex = intRegMap[reg];
193 assert(flatIndex < NumIntRegs);
198 flattenFloatIndex(int reg)
207 hSTickCompare = NULL;