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31 #ifndef __ARCH_SPARC_ISA_HH__
32 #define __ARCH_SPARC_ISA_HH__
34 #include "arch/sparc/registers.hh"
35 #include "arch/sparc/types.hh"
36 #include "config/full_system.hh"
37 #include "cpu/cpuevent.hh"
53 //uint64_t y; // Y (used in obsolete multiplication)
54 //uint8_t ccr; // Condition Code Register
55 uint8_t asi; // Address Space Identifier
56 uint64_t tick; // Hardware clock-tick counter
57 uint8_t fprs; // Floating-Point Register State
58 uint64_t gsr; // General Status Register
60 uint64_t tick_cmpr; // Hardware tick compare registers
61 uint64_t stick; // Hardware clock-tick counter
62 uint64_t stick_cmpr; // Hardware tick compare registers
65 /* Privileged Registers */
66 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
67 // previous trap level)
68 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
69 // previous trap level)
70 uint64_t tstate[MaxTL]; // Trap State
71 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
72 // on the previous level)
73 uint64_t tba; // Trap Base Address
75 uint16_t pstate; // Process State Register
76 uint8_t tl; // Trap Level
77 uint8_t pil; // Process Interrupt Register
78 uint8_t cwp; // Current Window Pointer
79 //uint8_t cansave; // Savable windows
80 //uint8_t canrestore; // Restorable windows
81 //uint8_t cleanwin; // Clean windows
82 //uint8_t otherwin; // Other windows
83 //uint8_t wstate; // Window State
84 uint8_t gl; // Global level register
86 /** Hyperprivileged Registers */
87 uint64_t hpstate; // Hyperprivileged State Register
88 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
90 uint64_t htba; // Hyperprivileged Trap Base Address register
91 uint64_t hstick_cmpr; // Hardware tick compare registers
93 uint64_t strandStatusReg;// Per strand status register
95 /** Floating point misc registers. */
96 uint64_t fsr; // Floating-Point State Register
98 /** MMU Internal Registers */
104 uint64_t scratchPad[8];
106 uint64_t cpu_mondo_head;
107 uint64_t cpu_mondo_tail;
108 uint64_t dev_mondo_head;
109 uint64_t dev_mondo_tail;
110 uint64_t res_error_head;
111 uint64_t res_error_tail;
112 uint64_t nres_error_head;
113 uint64_t nres_error_tail;
115 // These need to check the int_dis field and if 0 then
116 // set appropriate bit in softint and checkinterrutps on the cpu
118 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
119 MiscReg readFSReg(int miscReg, ThreadContext * tc);
121 // Update interrupt state on softint or pil change
122 void checkSoftInt(ThreadContext *tc);
124 /** Process a tick compare event and generate an interrupt on the cpu if
126 void processTickCompare(ThreadContext *tc);
127 void processSTickCompare(ThreadContext *tc);
128 void processHSTickCompare(ThreadContext *tc);
130 typedef CpuEventWrapper<ISA,
131 &ISA::processTickCompare> TickCompareEvent;
132 TickCompareEvent *tickCompare;
134 typedef CpuEventWrapper<ISA,
135 &ISA::processSTickCompare> STickCompareEvent;
136 STickCompareEvent *sTickCompare;
138 typedef CpuEventWrapper<ISA,
139 &ISA::processHSTickCompare> HSTickCompareEvent;
140 HSTickCompareEvent *hSTickCompare;
143 static const int NumGlobalRegs = 8;
144 static const int NumWindowedRegs = 24;
145 static const int WindowOverlap = 8;
147 static const int TotalGlobals = (MaxGL + 1) * NumGlobalRegs;
148 static const int RegsPerWindow = NumWindowedRegs - WindowOverlap;
149 static const int TotalWindowed = NWindows * RegsPerWindow;
151 enum InstIntRegOffsets {
152 CurrentGlobalsOffset = 0,
153 CurrentWindowOffset = CurrentGlobalsOffset + NumGlobalRegs,
154 MicroIntOffset = CurrentWindowOffset + NumWindowedRegs,
155 NextGlobalsOffset = MicroIntOffset + NumMicroIntRegs,
156 NextWindowOffset = NextGlobalsOffset + NumGlobalRegs,
157 PreviousGlobalsOffset = NextWindowOffset + NumWindowedRegs,
158 PreviousWindowOffset = PreviousGlobalsOffset + NumGlobalRegs,
159 TotalInstIntRegs = PreviousWindowOffset + NumWindowedRegs
162 RegIndex intRegMap[TotalInstIntRegs];
163 void installWindow(int cwp, int offset);
164 void installGlobals(int gl, int offset);
171 void serialize(EventManager *em, std::ostream & os);
173 void unserialize(EventManager *em, Checkpoint *cp,
174 const std::string & section);
178 bool isHyperPriv() { return (hpstate & (1 << 2)); }
179 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
180 bool isNonPriv() { return !isPriv(); }
184 MiscReg readMiscRegNoEffect(int miscReg);
185 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
187 void setMiscRegNoEffect(int miscReg, const MiscReg val);
188 void setMiscReg(int miscReg, const MiscReg val,
192 flattenIntIndex(int reg)
194 assert(reg < TotalInstIntRegs);
195 RegIndex flatIndex = intRegMap[reg];
196 assert(flatIndex < NumIntRegs);
201 flattenFloatIndex(int reg)