Registers: Add an ISA object which replaces the MiscRegFile.
[gem5.git] / src / arch / sparc / isa.hh
1 /*
2 * Copyright (c) 2009 The Regents of The University of Michigan
3 * All rights reserved.
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9 * redistributions in binary form must reproduce the above copyright
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13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __ARCH_SPARC_ISA_HH__
32 #define __ARCH_SPARC_ISA_HH__
33
34 #include "arch/sparc/miscregfile.hh"
35 #include "arch/sparc/types.hh"
36
37 class Checkpoint;
38 class EventManager;
39
40 namespace SparcISA
41 {
42 class ISA
43 {
44 protected:
45 MiscRegFile miscRegFile;
46
47 public:
48
49 int instAsid()
50 {
51 return miscRegFile.getInstAsid();
52 }
53
54 int dataAsid()
55 {
56 return miscRegFile.getDataAsid();
57 }
58
59 void clear();
60
61 MiscReg readMiscRegNoEffect(int miscReg);
62 MiscReg readMiscReg(int miscReg, ThreadContext *tc);
63
64 void setMiscRegNoEffect(int miscReg, const MiscReg val);
65 void setMiscReg(int miscReg, const MiscReg val,
66 ThreadContext *tc);
67
68 int flattenIntIndex(int reg);
69
70 int
71 flattenFloatIndex(int reg)
72 {
73 return reg;
74 }
75
76 void serialize(EventManager *em, std::ostream &os);
77 void unserialize(EventManager *em, Checkpoint *cp,
78 const std::string &section);
79
80 ISA()
81 {
82 clear();
83 }
84 };
85 }
86
87 #endif