Merge zizzer:/bk/newmem
[gem5.git] / src / arch / sparc / isa_traits.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33 #define __ARCH_SPARC_ISA_TRAITS_HH__
34
35 #include "arch/sparc/types.hh"
36 #include "arch/sparc/sparc_traits.hh"
37 #include "config/full_system.hh"
38 #include "sim/host.hh"
39
40 class StaticInstPtr;
41
42 namespace BigEndianGuest {}
43
44 namespace SparcISA
45 {
46 class RegFile;
47
48 const int MachineBytes = 8;
49
50 //This makes sure the big endian versions of certain functions are used.
51 using namespace BigEndianGuest;
52
53 // SPARC has a delay slot
54 #define ISA_HAS_DELAY_SLOT 1
55
56 // SPARC NOP (sethi %(hi(0), g0)
57 const MachInst NoopMachInst = 0x01000000;
58
59 // These enumerate all the registers for dependence tracking.
60 enum DependenceTags {
61 FP_Base_DepTag = 32*3+8,
62 Ctrl_Base_DepTag = FP_Base_DepTag + 64
63 };
64
65 // semantically meaningful register indices
66 const int ZeroReg = 0; // architecturally meaningful
67 // the rest of these depend on the ABI
68 const int StackPointerReg = 14;
69 const int ReturnAddressReg = 31; // post call, precall is 15
70 const int ReturnValueReg = 8; // Post return, 24 is pre-return.
71 const int FramePointerReg = 30;
72 const int ArgumentReg0 = 8;
73 const int ArgumentReg1 = 9;
74 const int ArgumentReg2 = 10;
75 const int ArgumentReg3 = 11;
76 const int ArgumentReg4 = 12;
77 const int ArgumentReg5 = 13;
78 // Some OS syscall use a second register (o1) to return a second value
79 const int SyscallPseudoReturnReg = ArgumentReg1;
80
81 //XXX These numbers are bogus
82 const int MaxInstSrcRegs = 8;
83 const int MaxInstDestRegs = 9;
84
85 //8K. This value is implmentation specific; and should probably
86 //be somewhere else.
87 const int LogVMPageSize = 13;
88 const int VMPageSize = (1 << LogVMPageSize);
89
90 //Why does both the previous set of constants and this one exist?
91 const int PageShift = 13;
92 const int PageBytes = 1ULL << PageShift;
93
94 const int BranchPredAddrShiftAmt = 2;
95
96 StaticInstPtr decodeInst(ExtMachInst);
97
98 #if FULL_SYSTEM
99 // I don't know what it's for, so I don't
100 // know what SPARC's value should be
101 // For loading... XXX This maybe could be USegEnd?? --ali
102 const Addr LoadAddrMask = ULL(0xffffffffff);
103
104 /////////// TLB Stuff ////////////
105 const Addr StartVAddrHole = ULL(0x0000800000000000);
106 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
107 const Addr VAddrAMask = ULL(0xFFFFFFFF);
108 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
109 const Addr BytesInPageMask = ULL(0x1FFF);
110
111 #endif
112 }
113
114 #endif // __ARCH_SPARC_ISA_TRAITS_HH__