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32 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
33 #define __ARCH_SPARC_ISA_TRAITS_HH__
35 #include "arch/sparc/sparc_traits.hh"
36 #include "arch/sparc/types.hh"
37 #include "base/types.hh"
38 #include "cpu/static_inst_fwd.hh"
40 namespace BigEndianGuest {}
44 // This makes sure the big endian versions of certain functions are used.
45 using namespace BigEndianGuest;
47 // SPARC has a delay slot
48 #define ISA_HAS_DELAY_SLOT 1
50 // SPARC NOP (sethi %(hi(0), g0)
51 const MachInst NoopMachInst = 0x01000000;
53 // real address virtual mapping
54 // sort of like alpha super page, but less frequently used
55 const Addr SegKPMEnd = ULL(0xfffffffc00000000);
56 const Addr SegKPMBase = ULL(0xfffffac000000000);
58 const Addr PageShift = 13;
59 const Addr PageBytes = ULL(1) << PageShift;
61 StaticInstPtr decodeInst(ExtMachInst);
63 /////////// TLB Stuff ////////////
64 const Addr StartVAddrHole = ULL(0x0000800000000000);
65 const Addr EndVAddrHole = ULL(0xFFFF7FFFFFFFFFFF);
66 const Addr VAddrAMask = ULL(0xFFFFFFFF);
67 const Addr PAddrImplMask = ULL(0x000000FFFFFFFFFF);
68 const Addr BytesInPageMask = ULL(0x1FFF);
82 // Memory accesses cannot be unaligned
83 const bool HasUnalignedMemAcc = false;
85 const bool CurThreadInfoImplemented = false;
86 const int CurThreadInfoReg = -1;
90 #endif // __ARCH_SPARC_ISA_TRAITS_HH__