src/arch/sparc/isa_traits.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  */
  30
  31 #ifndef __ARCH_SPARC_ISA_TRAITS_HH__
  32 #define __ARCH_SPARC_ISA_TRAITS_HH__
  33
  34 #include "arch/sparc/types.hh"
  35 #include "base/misc.hh"
  36 #include "config/full_system.hh"
  37 #include "sim/host.hh"
  38
  39 class ThreadContext;
  40 class FastCPU;
  41 //class FullCPU;
  42 class Checkpoint;
  43
  44 class StaticInst;
  45 class StaticInstPtr;
  46
  47 namespace BigEndianGuest {}
  48
  49 #if FULL_SYSTEM
  50 #include "arch/sparc/isa_fullsys_traits.hh"
  51 #endif
  52
  53 namespace SparcISA
  54 {
  55     class RegFile;
  56
  57     //This makes sure the big endian versions of certain functions are used.
  58     using namespace BigEndianGuest;
  59
  60     //TODO this needs to be a SPARC Noop
  61     // Alpha UNOP (ldq_u r31,0(r0))
  62     const MachInst NoopMachInst = 0x2ffe0000;
  63
  64     const int NumIntRegs = 32;
  65     const int NumFloatRegs = 64;
  66     const int NumMiscRegs = 40;
  67
  68     // These enumerate all the registers for dependence tracking.
  69     enum DependenceTags {
  70         // 0..31 are the integer regs 0..31
  71         // 32..95 are the FP regs 0..31, i.e. use (reg + FP_Base_DepTag)
  72         FP_Base_DepTag = NumIntRegs,
  73         Ctrl_Base_DepTag = NumIntRegs + NumFloatRegs,
  74         //XXX These are here solely to get compilation and won't work
  75         Fpcr_DepTag = 0,
  76         Uniq_DepTag = 0
  77     };
  78
  79
  80     // MAXTL - maximum trap level
  81     const int MaxPTL = 2;
  82     const int MaxTL  = 6;
  83     const int MaxGL  = 3;
  84     const int MaxPGL = 2;
  85
  86     // NWINDOWS - number of register windows, can be 3 to 32
  87     const int NWindows = 32;
  88
  89     // semantically meaningful register indices
  90     const int ZeroReg = 0;      // architecturally meaningful
  91     // the rest of these depend on the ABI
  92     const int StackPointerReg = 14;
  93     const int ReturnAddressReg = 31; // post call, precall is 15
  94     const int ReturnValueReg = 8; // Post return, 24 is pre-return.
  95     const int FramePointerReg = 30;
  96     const int ArgumentReg0 = 8;
  97     const int ArgumentReg1 = 9;
  98     const int ArgumentReg2 = 10;
  99     const int ArgumentReg3 = 11;
 100     const int ArgumentReg4 = 12;
 101     const int ArgumentReg5 = 13;
 102     // Some OS syscall use a second register (o1) to return a second value
 103     const int SyscallPseudoReturnReg = ArgumentReg1;
 104
 105     //XXX These numbers are bogus
 106     const int MaxInstSrcRegs = 8;
 107     const int MaxInstDestRegs = 9;
 108
 109     //8K. This value is implmentation specific; and should probably
 110     //be somewhere else.
 111     const int LogVMPageSize = 13;
 112     const int VMPageSize = (1 << LogVMPageSize);
 113
 114     //Why does both the previous set of constants and this one exist?
 115     const int PageShift = 13;
 116     const int PageBytes = ULL(1) << PageShift;
 117
 118     const int BranchPredAddrShiftAmt = 2;
 119
 120     const int MachineBytes = 8;
 121     const int WordBytes = 4;
 122     const int HalfwordBytes = 2;
 123     const int ByteBytes = 1;
 124
 125     void serialize(std::ostream & os);
 126
 127     void unserialize(Checkpoint *cp, const std::string &section);
 128
 129     StaticInstPtr decodeInst(ExtMachInst);
 130
 131     // return a no-op instruction... used for instruction fetch faults
 132     extern const MachInst NoopMachInst;
 133 }
 134
 135 #endif // __ARCH_SPARC_ISA_TRAITS_HH__