src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  50          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51          "stick", "stick_cmpr",
  52          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
  54          "wstate",*/ "gl",
  55          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56          "hstick_cmpr",
  57          "fsr", "prictx", "secctx", "partId", "lsuCtrlReg",
  58          "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
  59          "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
  60          "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
  61          "nresErrorHead", "nresErrorTail", "TlbData" };
  62
  63     return miscRegName[index];
  64 }
  65
  66 enum RegMask
  67 {
  68         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  69 };
  70
  71 void MiscRegFile::clear()
  72 {
  73     //y = 0;
  74     //ccr = 0;
  75     asi = 0;
  76     tick = ULL(1) << 63;
  77     fprs = 0;
  78     gsr = 0;
  79     softint = 0;
  80     tick_cmpr = 0;
  81     stick = 0;
  82     stick_cmpr = 0;
  83     memset(tpc, 0, sizeof(tpc));
  84     memset(tnpc, 0, sizeof(tnpc));
  85     memset(tstate, 0, sizeof(tstate));
  86     memset(tt, 0, sizeof(tt));
  87     pstate = 0;
  88     tl = 0;
  89     pil = 0;
  90     cwp = 0;
  91     //cansave = 0;
  92     //canrestore = 0;
  93     //cleanwin = 0;
  94     //otherwin = 0;
  95     //wstate = 0;
  96     gl = 0;
  97     //In a T1, bit 11 is apparently always 1
  98     hpstate = (1 << 11);
  99     memset(htstate, 0, sizeof(htstate));
 100     hintp = 0;
 101     htba = 0;
 102     hstick_cmpr = 0;
 103     //This is set this way in Legion for some reason
 104     strandStatusReg = 0x50000;
 105     fsr = 0;
 106
 107     priContext = 0;
 108     secContext = 0;
 109     partId = 0;
 110     lsuCtrlReg = 0;
 111
 112     memset(scratchPad, 0, sizeof(scratchPad));
 113 #if FULL_SYSTEM
 114     tickCompare = NULL;
 115     sTickCompare = NULL;
 116     hSTickCompare = NULL;
 117 #endif
 118 }
 119
 120 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 121 {
 122
 123   // The three miscRegs are moved up from the switch statement
 124   // due to more frequent calls.
 125
 126   if (miscReg == MISCREG_GL)
 127     return gl;
 128   if (miscReg == MISCREG_CWP)
 129     return cwp;
 130   if (miscReg == MISCREG_TLB_DATA) {
 131     /* Package up all the data for the tlb:
 132      * 6666555555555544444444443333333333222222222211111111110000000000
 133      * 3210987654321098765432109876543210987654321098765432109876543210
 134      *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
 135      *                                                           ||||^red
 136      *                                                           |||^priv
 137      *                                                           ||^am
 138      *                                                           |^lsuim
 139      *                                                           ^lsudm
 140      */
 141     return bits((uint64_t)hpstate,2,2) |
 142            bits((uint64_t)hpstate,5,5) << 1 |
 143            bits((uint64_t)pstate,3,2) << 2 |
 144            bits((uint64_t)lsuCtrlReg,3,2) << 4 |
 145            bits((uint64_t)partId,7,0) << 8 |
 146            bits((uint64_t)tl,2,0) << 16 |
 147                 (uint64_t)priContext << 32 |
 148                 (uint64_t)secContext << 48;
 149   }
 150
 151     switch (miscReg) {
 152       //case MISCREG_TLB_DATA:
 153       //  [original contents see above]
 154       //case MISCREG_Y:
 155       //  return y;
 156       //case MISCREG_CCR:
 157       //  return ccr;
 158       case MISCREG_ASI:
 159         return asi;
 160       case MISCREG_FPRS:
 161         return fprs;
 162       case MISCREG_TICK:
 163         return tick;
 164       case MISCREG_PCR:
 165         panic("PCR not implemented\n");
 166       case MISCREG_PIC:
 167         panic("PIC not implemented\n");
 168       case MISCREG_GSR:
 169         return gsr;
 170       case MISCREG_SOFTINT:
 171         return softint;
 172       case MISCREG_TICK_CMPR:
 173         return tick_cmpr;
 174       case MISCREG_STICK:
 175         return stick;
 176       case MISCREG_STICK_CMPR:
 177         return stick_cmpr;
 178
 179         /** Privilged Registers */
 180       case MISCREG_TPC:
 181         return tpc[tl-1];
 182       case MISCREG_TNPC:
 183         return tnpc[tl-1];
 184       case MISCREG_TSTATE:
 185         return tstate[tl-1];
 186       case MISCREG_TT:
 187         return tt[tl-1];
 188       case MISCREG_PRIVTICK:
 189         panic("Priviliged access to tick registers not implemented\n");
 190       case MISCREG_TBA:
 191         return tba;
 192       case MISCREG_PSTATE:
 193         return pstate;
 194       case MISCREG_TL:
 195         return tl;
 196       case MISCREG_PIL:
 197         return pil;
 198       //CWP, GL moved
 199       //case MISCREG_CWP:
 200       //  return cwp;
 201       //case MISCREG_CANSAVE:
 202       //  return cansave;
 203       //case MISCREG_CANRESTORE:
 204       //  return canrestore;
 205       //case MISCREG_CLEANWIN:
 206       //  return cleanwin;
 207       //case MISCREG_OTHERWIN:
 208       //  return otherwin;
 209       //case MISCREG_WSTATE:
 210       //  return wstate;
 211       //case MISCREG_GL:
 212       //  return gl;
 213
 214         /** Hyper privileged registers */
 215       case MISCREG_HPSTATE:
 216         return hpstate;
 217       case MISCREG_HTSTATE:
 218         return htstate[tl-1];
 219       case MISCREG_HINTP:
 220         return hintp;
 221       case MISCREG_HTBA:
 222         return htba;
 223       case MISCREG_STRAND_STS_REG:
 224         return strandStatusReg;
 225       case MISCREG_HSTICK_CMPR:
 226         return hstick_cmpr;
 227
 228         /** Floating Point Status Register */
 229       case MISCREG_FSR:
 230         DPRINTF(MiscRegs, "FSR read as: %#x\n", fsr);
 231         return fsr;
 232
 233       case MISCREG_MMU_P_CONTEXT:
 234         return priContext;
 235       case MISCREG_MMU_S_CONTEXT:
 236         return secContext;
 237       case MISCREG_MMU_PART_ID:
 238         return partId;
 239       case MISCREG_MMU_LSU_CTRL:
 240         return lsuCtrlReg;
 241
 242       case MISCREG_SCRATCHPAD_R0:
 243         return scratchPad[0];
 244       case MISCREG_SCRATCHPAD_R1:
 245         return scratchPad[1];
 246       case MISCREG_SCRATCHPAD_R2:
 247         return scratchPad[2];
 248       case MISCREG_SCRATCHPAD_R3:
 249         return scratchPad[3];
 250       case MISCREG_SCRATCHPAD_R4:
 251         return scratchPad[4];
 252       case MISCREG_SCRATCHPAD_R5:
 253         return scratchPad[5];
 254       case MISCREG_SCRATCHPAD_R6:
 255         return scratchPad[6];
 256       case MISCREG_SCRATCHPAD_R7:
 257         return scratchPad[7];
 258       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 259         return cpu_mondo_head;
 260       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 261         return cpu_mondo_tail;
 262       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 263         return dev_mondo_head;
 264       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 265         return dev_mondo_tail;
 266       case MISCREG_QUEUE_RES_ERROR_HEAD:
 267         return res_error_head;
 268       case MISCREG_QUEUE_RES_ERROR_TAIL:
 269         return res_error_tail;
 270       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 271         return nres_error_head;
 272       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 273         return nres_error_tail;
 274       default:
 275         panic("Miscellaneous register %d not implemented\n", miscReg);
 276     }
 277 }
 278
 279 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 280 {
 281     switch (miscReg) {
 282         // tick and stick are aliased to each other in niagra
 283         // well store the tick data in stick and the interrupt bit in tick
 284       case MISCREG_STICK:
 285       case MISCREG_TICK:
 286       case MISCREG_PRIVTICK:
 287         // I'm not sure why legion ignores the lowest two bits, but we'll go
 288         // with it
 289         // change from curCycle() to instCount() until we're done with legion
 290         DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
 291                 tc->getCpuPtr()->instCount(), stick);
 292         return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
 293                mbits(tick,63,63);
 294       case MISCREG_FPRS:
 295         // in legion if fp is enabled du and dl are set
 296         return fprs | 0x3;
 297       case MISCREG_PCR:
 298       case MISCREG_PIC:
 299         panic("Performance Instrumentation not impl\n");
 300       case MISCREG_SOFTINT_CLR:
 301       case MISCREG_SOFTINT_SET:
 302         panic("Can read from softint clr/set\n");
 303       case MISCREG_SOFTINT:
 304       case MISCREG_TICK_CMPR:
 305       case MISCREG_STICK_CMPR:
 306       case MISCREG_HINTP:
 307       case MISCREG_HTSTATE:
 308       case MISCREG_HTBA:
 309       case MISCREG_HVER:
 310       case MISCREG_STRAND_STS_REG:
 311       case MISCREG_HSTICK_CMPR:
 312       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 313       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 314       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 315       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 316       case MISCREG_QUEUE_RES_ERROR_HEAD:
 317       case MISCREG_QUEUE_RES_ERROR_TAIL:
 318       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 319       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 320 #if FULL_SYSTEM
 321       case MISCREG_HPSTATE:
 322         return readFSReg(miscReg, tc);
 323 #else
 324       case MISCREG_HPSTATE:
 325         //HPSTATE is special because because sometimes in privilege
 326         //checks for instructions it will read HPSTATE to make sure
 327         //the priv. level is ok So, we'll just have to tell it it
 328         //isn't, instead of panicing.
 329         return 0;
 330
 331       panic("Accessing Fullsystem register %s in SE mode\n",
 332             getMiscRegName(miscReg));
 333 #endif
 334
 335     }
 336     return readRegNoEffect(miscReg);
 337 }
 338
 339 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 340 {
 341     switch (miscReg) {
 342 //      case MISCREG_Y:
 343 //        y = val;
 344 //        break;
 345 //      case MISCREG_CCR:
 346 //        ccr = val;
 347 //        break;
 348       case MISCREG_ASI:
 349         asi = val;
 350         break;
 351       case MISCREG_FPRS:
 352         fprs = val;
 353         break;
 354       case MISCREG_TICK:
 355         tick = val;
 356         break;
 357       case MISCREG_PCR:
 358         panic("PCR not implemented\n");
 359       case MISCREG_PIC:
 360         panic("PIC not implemented\n");
 361       case MISCREG_GSR:
 362         gsr = val;
 363         break;
 364       case MISCREG_SOFTINT:
 365         softint = val;
 366         break;
 367       case MISCREG_TICK_CMPR:
 368         tick_cmpr = val;
 369         break;
 370       case MISCREG_STICK:
 371         stick = val;
 372         break;
 373       case MISCREG_STICK_CMPR:
 374         stick_cmpr = val;
 375         break;
 376
 377         /** Privilged Registers */
 378       case MISCREG_TPC:
 379         tpc[tl-1] = val;
 380         break;
 381       case MISCREG_TNPC:
 382         tnpc[tl-1] = val;
 383         break;
 384       case MISCREG_TSTATE:
 385         tstate[tl-1] = val;
 386         break;
 387       case MISCREG_TT:
 388         tt[tl-1] = val;
 389         break;
 390       case MISCREG_PRIVTICK:
 391         panic("Priviliged access to tick regesiters not implemented\n");
 392       case MISCREG_TBA:
 393         // clear lower 7 bits on writes.
 394         tba = val & ULL(~0x7FFF);
 395         break;
 396       case MISCREG_PSTATE:
 397         pstate = (val & PSTATE_MASK);
 398         break;
 399       case MISCREG_TL:
 400         tl = val;
 401         break;
 402       case MISCREG_PIL:
 403         pil = val;
 404         break;
 405       case MISCREG_CWP:
 406         cwp = val;
 407         break;
 408 //      case MISCREG_CANSAVE:
 409 //        cansave = val;
 410 //        break;
 411 //      case MISCREG_CANRESTORE:
 412 //        canrestore = val;
 413 //        break;
 414 //      case MISCREG_CLEANWIN:
 415 //        cleanwin = val;
 416 //        break;
 417 //      case MISCREG_OTHERWIN:
 418 //        otherwin = val;
 419 //        break;
 420 //      case MISCREG_WSTATE:
 421 //        wstate = val;
 422 //        break;
 423       case MISCREG_GL:
 424         gl = val;
 425         break;
 426
 427         /** Hyper privileged registers */
 428       case MISCREG_HPSTATE:
 429         hpstate = val;
 430         break;
 431       case MISCREG_HTSTATE:
 432         htstate[tl-1] = val;
 433         break;
 434       case MISCREG_HINTP:
 435         hintp = val;
 436       case MISCREG_HTBA:
 437         htba = val;
 438         break;
 439       case MISCREG_STRAND_STS_REG:
 440         strandStatusReg = val;
 441         break;
 442       case MISCREG_HSTICK_CMPR:
 443         hstick_cmpr = val;
 444         break;
 445
 446         /** Floating Point Status Register */
 447       case MISCREG_FSR:
 448         fsr = val;
 449         DPRINTF(MiscRegs, "FSR written with: %#x\n", fsr);
 450         break;
 451
 452       case MISCREG_MMU_P_CONTEXT:
 453         priContext = val;
 454         break;
 455       case MISCREG_MMU_S_CONTEXT:
 456         secContext = val;
 457         break;
 458       case MISCREG_MMU_PART_ID:
 459         partId = val;
 460         break;
 461       case MISCREG_MMU_LSU_CTRL:
 462         lsuCtrlReg = val;
 463         break;
 464
 465       case MISCREG_SCRATCHPAD_R0:
 466         scratchPad[0] = val;
 467         break;
 468       case MISCREG_SCRATCHPAD_R1:
 469         scratchPad[1] = val;
 470         break;
 471       case MISCREG_SCRATCHPAD_R2:
 472         scratchPad[2] = val;
 473         break;
 474       case MISCREG_SCRATCHPAD_R3:
 475         scratchPad[3] = val;
 476         break;
 477       case MISCREG_SCRATCHPAD_R4:
 478         scratchPad[4] = val;
 479         break;
 480       case MISCREG_SCRATCHPAD_R5:
 481         scratchPad[5] = val;
 482         break;
 483       case MISCREG_SCRATCHPAD_R6:
 484         scratchPad[6] = val;
 485         break;
 486       case MISCREG_SCRATCHPAD_R7:
 487         scratchPad[7] = val;
 488         break;
 489       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 490         cpu_mondo_head = val;
 491         break;
 492       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 493         cpu_mondo_tail = val;
 494         break;
 495       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 496         dev_mondo_head = val;
 497         break;
 498       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 499         dev_mondo_tail = val;
 500         break;
 501       case MISCREG_QUEUE_RES_ERROR_HEAD:
 502         res_error_head = val;
 503         break;
 504       case MISCREG_QUEUE_RES_ERROR_TAIL:
 505         res_error_tail = val;
 506         break;
 507       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 508         nres_error_head = val;
 509         break;
 510       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 511         nres_error_tail = val;
 512         break;
 513       default:
 514         panic("Miscellaneous register %d not implemented\n", miscReg);
 515     }
 516 }
 517
 518 void MiscRegFile::setReg(int miscReg,
 519         const MiscReg &val, ThreadContext * tc)
 520 {
 521     MiscReg new_val = val;
 522
 523     switch (miscReg) {
 524       case MISCREG_STICK:
 525       case MISCREG_TICK:
 526         // stick and tick are same thing on niagra
 527         // use stick for offset and tick for holding intrrupt bit
 528         stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
 529         tick = mbits(val,63,63);
 530         DPRINTF(Timer, "Writing TICK=%#X\n", val);
 531         break;
 532       case MISCREG_FPRS:
 533         //Configure the fpu based on the fprs
 534         break;
 535       case MISCREG_PCR:
 536         //Set up performance counting based on pcr value
 537         break;
 538       case MISCREG_PSTATE:
 539         pstate = val & PSTATE_MASK;
 540         return;
 541       case MISCREG_TL:
 542         tl = val;
 543 #if FULL_SYSTEM
 544         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
 545             tc->getCpuPtr()->postInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 546         else
 547             tc->getCpuPtr()->clearInterrupt(IT_TRAP_LEVEL_ZERO, 0);
 548 #endif
 549         return;
 550       case MISCREG_CWP:
 551         new_val = val >= NWindows ? NWindows - 1 : val;
 552         if (val >= NWindows)
 553             new_val = NWindows - 1;
 554         break;
 555       case MISCREG_GL:
 556         break;
 557       case MISCREG_PIL:
 558       case MISCREG_SOFTINT:
 559       case MISCREG_SOFTINT_SET:
 560       case MISCREG_SOFTINT_CLR:
 561       case MISCREG_TICK_CMPR:
 562       case MISCREG_STICK_CMPR:
 563       case MISCREG_HINTP:
 564       case MISCREG_HTSTATE:
 565       case MISCREG_HTBA:
 566       case MISCREG_HVER:
 567       case MISCREG_STRAND_STS_REG:
 568       case MISCREG_HSTICK_CMPR:
 569       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 570       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 571       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 572       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 573       case MISCREG_QUEUE_RES_ERROR_HEAD:
 574       case MISCREG_QUEUE_RES_ERROR_TAIL:
 575       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 576       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 577 #if FULL_SYSTEM
 578       case MISCREG_HPSTATE:
 579         setFSReg(miscReg, val, tc);
 580         return;
 581 #else
 582       case MISCREG_HPSTATE:
 583         //HPSTATE is special because normal trap processing saves HPSTATE when
 584         //it goes into a trap, and restores it when it returns.
 585         return;
 586       panic("Accessing Fullsystem register %s to %#x in SE mode\n",
 587             getMiscRegName(miscReg), val);
 588 #endif
 589     }
 590     setRegNoEffect(miscReg, new_val);
 591 }
 592
 593 void
 594 MiscRegFile::serialize(EventManager *em, std::ostream &os)
 595 {
 596     SERIALIZE_SCALAR(asi);
 597     SERIALIZE_SCALAR(tick);
 598     SERIALIZE_SCALAR(fprs);
 599     SERIALIZE_SCALAR(gsr);
 600     SERIALIZE_SCALAR(softint);
 601     SERIALIZE_SCALAR(tick_cmpr);
 602     SERIALIZE_SCALAR(stick);
 603     SERIALIZE_SCALAR(stick_cmpr);
 604     SERIALIZE_ARRAY(tpc,MaxTL);
 605     SERIALIZE_ARRAY(tnpc,MaxTL);
 606     SERIALIZE_ARRAY(tstate,MaxTL);
 607     SERIALIZE_ARRAY(tt,MaxTL);
 608     SERIALIZE_SCALAR(tba);
 609     SERIALIZE_SCALAR(pstate);
 610     SERIALIZE_SCALAR(tl);
 611     SERIALIZE_SCALAR(pil);
 612     SERIALIZE_SCALAR(cwp);
 613     SERIALIZE_SCALAR(gl);
 614     SERIALIZE_SCALAR(hpstate);
 615     SERIALIZE_ARRAY(htstate,MaxTL);
 616     SERIALIZE_SCALAR(hintp);
 617     SERIALIZE_SCALAR(htba);
 618     SERIALIZE_SCALAR(hstick_cmpr);
 619     SERIALIZE_SCALAR(strandStatusReg);
 620     SERIALIZE_SCALAR(fsr);
 621     SERIALIZE_SCALAR(priContext);
 622     SERIALIZE_SCALAR(secContext);
 623     SERIALIZE_SCALAR(partId);
 624     SERIALIZE_SCALAR(lsuCtrlReg);
 625     SERIALIZE_ARRAY(scratchPad,8);
 626     SERIALIZE_SCALAR(cpu_mondo_head);
 627     SERIALIZE_SCALAR(cpu_mondo_tail);
 628     SERIALIZE_SCALAR(dev_mondo_head);
 629     SERIALIZE_SCALAR(dev_mondo_tail);
 630     SERIALIZE_SCALAR(res_error_head);
 631     SERIALIZE_SCALAR(res_error_tail);
 632     SERIALIZE_SCALAR(nres_error_head);
 633     SERIALIZE_SCALAR(nres_error_tail);
 634 #if FULL_SYSTEM
 635     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 636     ThreadContext *tc = NULL;
 637     BaseCPU *cpu = NULL;
 638     int tc_num = 0;
 639     bool tick_intr_sched = true;
 640
 641     if (tickCompare)
 642         tc = tickCompare->getTC();
 643     else if (sTickCompare)
 644         tc = sTickCompare->getTC();
 645     else if (hSTickCompare)
 646         tc = hSTickCompare->getTC();
 647     else
 648         tick_intr_sched = false;
 649
 650     SERIALIZE_SCALAR(tick_intr_sched);
 651
 652     if (tc) {
 653         cpu = tc->getCpuPtr();
 654         tc_num = cpu->findContext(tc);
 655         if (tickCompare && tickCompare->scheduled())
 656             tick_cmp = tickCompare->when();
 657         if (sTickCompare && sTickCompare->scheduled())
 658             stick_cmp = sTickCompare->when();
 659         if (hSTickCompare && hSTickCompare->scheduled())
 660             hstick_cmp = hSTickCompare->when();
 661
 662         SERIALIZE_OBJPTR(cpu);
 663         SERIALIZE_SCALAR(tc_num);
 664         SERIALIZE_SCALAR(tick_cmp);
 665         SERIALIZE_SCALAR(stick_cmp);
 666         SERIALIZE_SCALAR(hstick_cmp);
 667     }
 668 #endif
 669 }
 670
 671 void
 672 MiscRegFile::unserialize(EventManager *em, Checkpoint *cp,
 673     const string &section)
 674 {
 675     UNSERIALIZE_SCALAR(asi);
 676     UNSERIALIZE_SCALAR(tick);
 677     UNSERIALIZE_SCALAR(fprs);
 678     UNSERIALIZE_SCALAR(gsr);
 679     UNSERIALIZE_SCALAR(softint);
 680     UNSERIALIZE_SCALAR(tick_cmpr);
 681     UNSERIALIZE_SCALAR(stick);
 682     UNSERIALIZE_SCALAR(stick_cmpr);
 683     UNSERIALIZE_ARRAY(tpc,MaxTL);
 684     UNSERIALIZE_ARRAY(tnpc,MaxTL);
 685     UNSERIALIZE_ARRAY(tstate,MaxTL);
 686     UNSERIALIZE_ARRAY(tt,MaxTL);
 687     UNSERIALIZE_SCALAR(tba);
 688     UNSERIALIZE_SCALAR(pstate);
 689     UNSERIALIZE_SCALAR(tl);
 690     UNSERIALIZE_SCALAR(pil);
 691     UNSERIALIZE_SCALAR(cwp);
 692     UNSERIALIZE_SCALAR(gl);
 693     UNSERIALIZE_SCALAR(hpstate);
 694     UNSERIALIZE_ARRAY(htstate,MaxTL);
 695     UNSERIALIZE_SCALAR(hintp);
 696     UNSERIALIZE_SCALAR(htba);
 697     UNSERIALIZE_SCALAR(hstick_cmpr);
 698     UNSERIALIZE_SCALAR(strandStatusReg);
 699     UNSERIALIZE_SCALAR(fsr);
 700     UNSERIALIZE_SCALAR(priContext);
 701     UNSERIALIZE_SCALAR(secContext);
 702     UNSERIALIZE_SCALAR(partId);
 703     UNSERIALIZE_SCALAR(lsuCtrlReg);
 704     UNSERIALIZE_ARRAY(scratchPad,8);
 705     UNSERIALIZE_SCALAR(cpu_mondo_head);
 706     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 707     UNSERIALIZE_SCALAR(dev_mondo_head);
 708     UNSERIALIZE_SCALAR(dev_mondo_tail);
 709     UNSERIALIZE_SCALAR(res_error_head);
 710     UNSERIALIZE_SCALAR(res_error_tail);
 711     UNSERIALIZE_SCALAR(nres_error_head);
 712     UNSERIALIZE_SCALAR(nres_error_tail);
 713
 714 #if FULL_SYSTEM
 715     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 716     ThreadContext *tc = NULL;
 717     BaseCPU *cpu = NULL;
 718     int tc_num;
 719     bool tick_intr_sched;
 720     UNSERIALIZE_SCALAR(tick_intr_sched);
 721     if (tick_intr_sched) {
 722         UNSERIALIZE_OBJPTR(cpu);
 723         if (cpu) {
 724             UNSERIALIZE_SCALAR(tc_num);
 725             UNSERIALIZE_SCALAR(tick_cmp);
 726             UNSERIALIZE_SCALAR(stick_cmp);
 727             UNSERIALIZE_SCALAR(hstick_cmp);
 728             tc = cpu->getContext(tc_num);
 729
 730             if (tick_cmp) {
 731                 tickCompare = new TickCompareEvent(this, tc);
 732                 em->schedule(tickCompare, tick_cmp);
 733             }
 734             if (stick_cmp)  {
 735                 sTickCompare = new STickCompareEvent(this, tc);
 736                 em->schedule(sTickCompare, stick_cmp);
 737             }
 738             if (hstick_cmp)  {
 739                 hSTickCompare = new HSTickCompareEvent(this, tc);
 740                 em->schedule(hSTickCompare, hstick_cmp);
 741             }
 742         }
 743     }
 744
 745  #endif
 746 }