src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/miscregfile.hh"
  33 #include "base/trace.hh"
  34 #include "cpu/base.hh"
  35 #include "cpu/thread_context.hh"
  36
  37 using namespace SparcISA;
  38 using namespace std;
  39
  40 class Checkpoint;
  41
  42 //These functions map register indices to names
  43 string SparcISA::getMiscRegName(RegIndex index)
  44 {
  45     static::string miscRegName[NumMiscRegs] =
  46         {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
  47          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  48          "stick", "stick_cmpr",
  49          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  50          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  51          "wstate", "gl",
  52          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  53          "hstick_cmpr",
  54          "fsr"};
  55     return miscRegName[index];
  56 }
  57
  58 #if FULL_SYSTEM
  59
  60 //XXX These need an implementation someplace
  61 /** Fullsystem only register version of ReadRegWithEffect() */
  62 MiscReg MiscRegFile::readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
  63 /** Fullsystem only register version of SetRegWithEffect() */
  64 Fault MiscRegFile::setFSRegWithEffect(int miscReg, const MiscReg &val,
  65         ThreadContext * tc);
  66 #endif
  67
  68 void MiscRegFile::reset()
  69 {
  70     pstateFields.pef = 0; //No FPU
  71     //pstateFields.pef = 1; //FPU
  72 #if FULL_SYSTEM
  73     //For SPARC, when a system is first started, there is a power
  74     //on reset Trap which sets the processor into the following state.
  75     //Bits that aren't set aren't defined on startup.
  76     tl = MaxTL;
  77     gl = MaxGL;
  78
  79     tickFields.counter = 0; //The TICK register is unreadable bya
  80     tickFields.npt = 1; //The TICK register is unreadable by by !priv
  81
  82     softint = 0; // Clear all the soft interrupt bits
  83     tick_cmprFields.int_dis = 1; // disable timer compare interrupts
  84     tick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
  85     stickFields.npt = 1; //The TICK register is unreadable by by !priv
  86     stick_cmprFields.int_dis = 1; // disable timer compare interrupts
  87     stick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
  88
  89
  90     tt[tl] = power_on_reset;
  91     pstate = 0; // fields 0 but pef
  92     pstateFields.pef = 1;
  93
  94     hpstate = 0;
  95     hpstateFields.red = 1;
  96     hpstateFields.hpriv = 1;
  97     hpstateFields.tlz = 0; // this is a guess
  98     hintp = 0; // no interrupts pending
  99     hstick_cmprFields.int_dis = 1; // disable timer compare interrupts
 100     hstick_cmprFields.tick_cmpr = 0; // Reset to 0 for pretty printing
 101 #else
 102 /*          //This sets up the initial state of the processor for usermode processes
 103     pstateFields.priv = 0; //Process runs in user mode
 104     pstateFields.ie = 1; //Interrupts are enabled
 105     fsrFields.rd = 0; //Round to nearest
 106     fsrFields.tem = 0; //Floating point traps not enabled
 107     fsrFields.ns = 0; //Non standard mode off
 108     fsrFields.qne = 0; //Floating point queue is empty
 109     fsrFields.aexc = 0; //No accrued exceptions
 110     fsrFields.cexc = 0; //No current exceptions
 111
 112     //Register window management registers
 113     otherwin = 0; //No windows contain info from other programs
 114     canrestore = 0; //There are no windows to pop
 115     cansave = MaxTL - 2; //All windows are available to save into
 116     cleanwin = MaxTL;*/
 117 #endif
 118 }
 119
 120 MiscReg MiscRegFile::readReg(int miscReg)
 121 {
 122     switch (miscReg) {
 123         case MISCREG_Y:
 124           return y;
 125         case MISCREG_CCR:
 126           return ccr;
 127         case MISCREG_ASI:
 128           return asi;
 129         case MISCREG_FPRS:
 130           return fprs;
 131         case MISCREG_TICK:
 132            return tick;
 133         case MISCREG_PCR:
 134         case MISCREG_PIC:
 135           panic("ASR number %d not implemented\n", miscReg - AsrStart);
 136         case MISCREG_GSR:
 137           return gsr;
 138         case MISCREG_SOFTINT:
 139            return softint;
 140         case MISCREG_TICK_CMPR:
 141            return tick_cmpr;
 142         case MISCREG_STICK:
 143            return stick;
 144         case MISCREG_STICK_CMPR:
 145            return stick_cmpr;
 146
 147         /** Privilged Registers */
 148         case MISCREG_TPC:
 149           return tpc[tl-1];
 150         case MISCREG_TNPC:
 151           return tnpc[tl-1];
 152         case MISCREG_TSTATE:
 153           return tstate[tl-1];
 154         case MISCREG_TT:
 155           return tt[tl-1];
 156         case MISCREG_PRIVTICK:
 157           panic("Priviliged access to tick registers not implemented\n");
 158         case MISCREG_TBA:
 159           return tba;
 160         case MISCREG_PSTATE:
 161           return pstate;
 162         case MISCREG_TL:
 163           return tl;
 164         case MISCREG_PIL:
 165           return pil;
 166         case MISCREG_CWP:
 167           return cwp;
 168         case MISCREG_CANSAVE:
 169           return cansave;
 170         case MISCREG_CANRESTORE:
 171           return canrestore;
 172         case MISCREG_CLEANWIN:
 173           return cleanwin;
 174         case MISCREG_OTHERWIN:
 175           return otherwin;
 176         case MISCREG_WSTATE:
 177           return wstate;
 178         case MISCREG_GL:
 179           return gl;
 180
 181         /** Hyper privileged registers */
 182         case MISCREG_HPSTATE:
 183           return hpstate;
 184         case MISCREG_HTSTATE:
 185           return htstate[tl-1];
 186         case MISCREG_HINTP:
 187           panic("HINTP not implemented\n");
 188         case MISCREG_HTBA:
 189           return htba;
 190         case MISCREG_HVER:
 191           return NWindows | MaxTL << 8 | MaxGL << 16;
 192         case MISCREG_STRAND_STS_REG:
 193           return strandStatusReg;
 194         case MISCREG_HSTICK_CMPR:
 195           return hstick_cmpr;
 196
 197         /** Floating Point Status Register */
 198         case MISCREG_FSR:
 199           return fsr;
 200         default:
 201           panic("Miscellaneous register %d not implemented\n", miscReg);
 202     }
 203 }
 204
 205 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 206 {
 207     switch (miscReg) {
 208         case MISCREG_TICK:
 209         case MISCREG_PRIVTICK:
 210           return tc->getCpuPtr()->curCycle() - tickFields.counter |
 211               tickFields.npt << 63;
 212         case MISCREG_FPRS:
 213           panic("FPU not implemented\n");
 214         case MISCREG_PCR:
 215         case MISCREG_PIC:
 216           panic("Performance Instrumentation not impl\n");
 217
 218         /** Floating Point Status Register */
 219         case MISCREG_FSR:
 220           panic("Floating Point not implemented\n");
 221     }
 222     return readReg(miscReg);
 223 }
 224
 225 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 226 {
 227     switch (miscReg) {
 228         case MISCREG_Y:
 229           y = val;
 230           break;
 231         case MISCREG_CCR:
 232           ccr = val;
 233           break;
 234         case MISCREG_ASI:
 235           asi = val;
 236           break;
 237         case MISCREG_FPRS:
 238           fprs = val;
 239           break;
 240         case MISCREG_TICK:
 241           tick = val;
 242           break;
 243         case MISCREG_PCR:
 244         case MISCREG_PIC:
 245           panic("ASR number %d not implemented\n", miscReg - AsrStart);
 246         case MISCREG_GSR:
 247           gsr = val;
 248           break;
 249         case MISCREG_SOFTINT:
 250           softint = val;
 251           break;
 252         case MISCREG_TICK_CMPR:
 253           tick_cmpr = val;
 254           break;
 255         case MISCREG_STICK:
 256           stick = val;
 257           break;
 258         case MISCREG_STICK_CMPR:
 259           stick_cmpr = val;
 260           break;
 261
 262         /** Privilged Registers */
 263         case MISCREG_TPC:
 264           tpc[tl-1] = val;
 265           break;
 266         case MISCREG_TNPC:
 267           tnpc[tl-1] = val;
 268           break;
 269         case MISCREG_TSTATE:
 270           tstate[tl-1] = val;
 271           break;
 272         case MISCREG_TT:
 273           tt[tl-1] = val;
 274           break;
 275         case MISCREG_PRIVTICK:
 276           panic("Priviliged access to tick regesiters not implemented\n");
 277         case MISCREG_TBA:
 278           // clear lower 7 bits on writes.
 279           tba = val & ULL(~0x7FFF);
 280           break;
 281         case MISCREG_PSTATE:
 282           pstate = val;
 283           break;
 284         case MISCREG_TL:
 285           tl = val;
 286           break;
 287         case MISCREG_PIL:
 288           pil = val;
 289           break;
 290         case MISCREG_CWP:
 291           cwp = val;
 292           break;
 293         case MISCREG_CANSAVE:
 294           cansave = val;
 295           break;
 296         case MISCREG_CANRESTORE:
 297           canrestore = val;
 298           break;
 299         case MISCREG_CLEANWIN:
 300           cleanwin = val;
 301           break;
 302         case MISCREG_OTHERWIN:
 303           otherwin = val;
 304           break;
 305         case MISCREG_WSTATE:
 306           wstate = val;
 307           break;
 308         case MISCREG_GL:
 309           gl = val;
 310           break;
 311
 312         /** Hyper privileged registers */
 313         case MISCREG_HPSTATE:
 314           hpstate = val;
 315           break;
 316         case MISCREG_HTSTATE:
 317           htstate[tl-1] = val;
 318           break;
 319         case MISCREG_HINTP:
 320           panic("HINTP not implemented\n");
 321         case MISCREG_HTBA:
 322           htba = val;
 323           break;
 324         case MISCREG_STRAND_STS_REG:
 325           strandStatusReg = val;
 326           break;
 327         case MISCREG_HSTICK_CMPR:
 328           hstick_cmpr = val;
 329           break;
 330
 331         /** Floating Point Status Register */
 332         case MISCREG_FSR:
 333           fsr = val;
 334           break;
 335         default:
 336           panic("Miscellaneous register %d not implemented\n", miscReg);
 337     }
 338 }
 339
 340 void MiscRegFile::setRegWithEffect(int miscReg,
 341         const MiscReg &val, ThreadContext * tc)
 342 {
 343     const uint64_t Bit64 = (1ULL << 63);
 344     switch (miscReg) {
 345         case MISCREG_TICK:
 346           tickFields.counter = tc->getCpuPtr()->curCycle() - val  & ~Bit64;
 347           tickFields.npt = val & Bit64 ? 1 : 0;
 348           break;
 349         case MISCREG_FPRS:
 350           //Configure the fpu based on the fprs
 351           break;
 352         case MISCREG_PCR:
 353           //Set up performance counting based on pcr value
 354           break;
 355         case MISCREG_CWP:
 356           tc->changeRegFileContext(CONTEXT_CWP, val);
 357           break;
 358         case MISCREG_GL:
 359           tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 360           break;
 361     }
 362     setReg(miscReg, val);
 363 }
 364
 365 void MiscRegFile::serialize(std::ostream & os)
 366 {
 367     SERIALIZE_SCALAR(pstate);
 368     SERIALIZE_SCALAR(tba);
 369     SERIALIZE_SCALAR(y);
 370     SERIALIZE_SCALAR(pil);
 371     SERIALIZE_SCALAR(gl);
 372     SERIALIZE_SCALAR(cwp);
 373     SERIALIZE_ARRAY(tt, MaxTL);
 374     SERIALIZE_SCALAR(ccr);
 375     SERIALIZE_SCALAR(asi);
 376     SERIALIZE_SCALAR(tl);
 377     SERIALIZE_ARRAY(tpc, MaxTL);
 378     SERIALIZE_ARRAY(tnpc, MaxTL);
 379     SERIALIZE_ARRAY(tstate, MaxTL);
 380     SERIALIZE_SCALAR(tick);
 381     SERIALIZE_SCALAR(cansave);
 382     SERIALIZE_SCALAR(canrestore);
 383     SERIALIZE_SCALAR(otherwin);
 384     SERIALIZE_SCALAR(cleanwin);
 385     SERIALIZE_SCALAR(wstate);
 386     SERIALIZE_SCALAR(fsr);
 387     SERIALIZE_SCALAR(fprs);
 388     SERIALIZE_SCALAR(hpstate);
 389     SERIALIZE_ARRAY(htstate, MaxTL);
 390     SERIALIZE_SCALAR(htba);
 391     SERIALIZE_SCALAR(hstick_cmpr);
 392 }
 393
 394 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 395 {
 396     UNSERIALIZE_SCALAR(pstate);
 397     UNSERIALIZE_SCALAR(tba);
 398     UNSERIALIZE_SCALAR(y);
 399     UNSERIALIZE_SCALAR(pil);
 400     UNSERIALIZE_SCALAR(gl);
 401     UNSERIALIZE_SCALAR(cwp);
 402     UNSERIALIZE_ARRAY(tt, MaxTL);
 403     UNSERIALIZE_SCALAR(ccr);
 404     UNSERIALIZE_SCALAR(asi);
 405     UNSERIALIZE_SCALAR(tl);
 406     UNSERIALIZE_ARRAY(tpc, MaxTL);
 407     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 408     UNSERIALIZE_ARRAY(tstate, MaxTL);
 409     UNSERIALIZE_SCALAR(tick);
 410     UNSERIALIZE_SCALAR(cansave);
 411     UNSERIALIZE_SCALAR(canrestore);
 412     UNSERIALIZE_SCALAR(otherwin);
 413     UNSERIALIZE_SCALAR(cleanwin);
 414     UNSERIALIZE_SCALAR(wstate);
 415     UNSERIALIZE_SCALAR(fsr);
 416     UNSERIALIZE_SCALAR(fprs);
 417     UNSERIALIZE_SCALAR(hpstate);
 418     UNSERIALIZE_ARRAY(htstate, MaxTL);
 419     UNSERIALIZE_SCALAR(htba);
 420     UNSERIALIZE_SCALAR(hstick_cmpr);
 421 }
 422