src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 #if FULL_SYSTEM
  41 #include "arch/sparc/system.hh"
  42 #endif
  43
  44 using namespace SparcISA;
  45 using namespace std;
  46
  47 class Checkpoint;
  48
  49 //These functions map register indices to names
  50 string SparcISA::getMiscRegName(RegIndex index)
  51 {
  52     static::string miscRegName[NumMiscRegs] =
  53         {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
  54          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  55          "stick", "stick_cmpr",
  56          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  57          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  58          "wstate", "gl",
  59          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  60          "hstick_cmpr",
  61          "fsr"};
  62     return miscRegName[index];
  63 }
  64
  65 enum RegMask
  66 {
  67         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  68 };
  69
  70 void MiscRegFile::clear()
  71 {
  72     y = 0;
  73     ccr = 0;
  74     asi = 0;
  75     tick = 0;
  76     fprs = 0;
  77     gsr = 0;
  78     softint = 0;
  79     tick_cmpr = 0;
  80     stick = 0;
  81     stick_cmpr = 0;
  82     memset(tpc, 0, sizeof(tpc));
  83     memset(tnpc, 0, sizeof(tnpc));
  84     memset(tstate, 0, sizeof(tstate));
  85     memset(tt, 0, sizeof(tt));
  86     pstate = 0;
  87     tl = 0;
  88     pil = 0;
  89     cwp = 0;
  90     cansave = 0;
  91     canrestore = 0;
  92     cleanwin = 0;
  93     otherwin = 0;
  94     wstate = 0;
  95     gl = 0;
  96     //In a T1, bit 11 is apparently always 1
  97     hpstate = (1 << 11);
  98     memset(htstate, 0, sizeof(htstate));
  99     hintp = 0;
 100     htba = 0;
 101     hstick_cmpr = 0;
 102     //This is set this way in Legion for some reason
 103     strandStatusReg = 0x50000;
 104     fsr = 0;
 105
 106     priContext = 0;
 107     secContext = 0;
 108     partId = 0;
 109     lsuCtrlReg = 0;
 110
 111     iTlbC0TsbPs0 = 0;
 112     iTlbC0TsbPs1 = 0;
 113     iTlbC0Config = 0;
 114     iTlbCXTsbPs0 = 0;
 115     iTlbCXTsbPs1 = 0;
 116     iTlbCXConfig = 0;
 117     iTlbSfsr = 0;
 118     iTlbTagAccess = 0;
 119
 120     dTlbC0TsbPs0 = 0;
 121     dTlbC0TsbPs1 = 0;
 122     dTlbC0Config = 0;
 123     dTlbCXTsbPs0 = 0;
 124     dTlbCXTsbPs1 = 0;
 125     dTlbCXConfig = 0;
 126     dTlbSfsr = 0;
 127     dTlbSfar = 0;
 128     dTlbTagAccess = 0;
 129
 130     memset(scratchPad, 0, sizeof(scratchPad));
 131 }
 132
 133 MiscReg MiscRegFile::readReg(int miscReg)
 134 {
 135     switch (miscReg) {
 136         case MISCREG_Y:
 137           return y;
 138         case MISCREG_CCR:
 139           return ccr;
 140         case MISCREG_ASI:
 141           return asi;
 142         case MISCREG_FPRS:
 143           return fprs;
 144         case MISCREG_TICK:
 145            return tick;
 146         case MISCREG_PCR:
 147           panic("PCR not implemented\n");
 148         case MISCREG_PIC:
 149           panic("PIC not implemented\n");
 150         case MISCREG_GSR:
 151           return gsr;
 152         case MISCREG_SOFTINT:
 153            return softint;
 154         case MISCREG_TICK_CMPR:
 155            return tick_cmpr;
 156         case MISCREG_STICK:
 157            return stick;
 158         case MISCREG_STICK_CMPR:
 159            return stick_cmpr;
 160
 161         /** Privilged Registers */
 162         case MISCREG_TPC:
 163           return tpc[tl-1];
 164         case MISCREG_TNPC:
 165           return tnpc[tl-1];
 166         case MISCREG_TSTATE:
 167           return tstate[tl-1];
 168         case MISCREG_TT:
 169           return tt[tl-1];
 170         case MISCREG_PRIVTICK:
 171           panic("Priviliged access to tick registers not implemented\n");
 172         case MISCREG_TBA:
 173           return tba;
 174         case MISCREG_PSTATE:
 175           return pstate;
 176         case MISCREG_TL:
 177           return tl;
 178         case MISCREG_PIL:
 179           return pil;
 180         case MISCREG_CWP:
 181           return cwp;
 182         case MISCREG_CANSAVE:
 183           return cansave;
 184         case MISCREG_CANRESTORE:
 185           return canrestore;
 186         case MISCREG_CLEANWIN:
 187           return cleanwin;
 188         case MISCREG_OTHERWIN:
 189           return otherwin;
 190         case MISCREG_WSTATE:
 191           return wstate;
 192         case MISCREG_GL:
 193           return gl;
 194
 195         /** Hyper privileged registers */
 196         case MISCREG_HPSTATE:
 197           return hpstate;
 198         case MISCREG_HTSTATE:
 199           return htstate[tl-1];
 200         case MISCREG_HINTP:
 201           panic("HINTP not implemented\n");
 202         case MISCREG_HTBA:
 203           return htba;
 204         case MISCREG_HVER:
 205           return NWindows | MaxTL << 8 | MaxGL << 16;
 206         case MISCREG_STRAND_STS_REG:
 207           return strandStatusReg;
 208         case MISCREG_HSTICK_CMPR:
 209           return hstick_cmpr;
 210
 211         /** Floating Point Status Register */
 212         case MISCREG_FSR:
 213           return fsr;
 214
 215         case MISCREG_MMU_P_CONTEXT:
 216           return priContext;
 217         case MISCREG_MMU_S_CONTEXT:
 218           return secContext;
 219         case MISCREG_MMU_PART_ID:
 220           return partId;
 221         case MISCREG_MMU_LSU_CTRL:
 222           return lsuCtrlReg;
 223
 224         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 225           return iTlbC0TsbPs0;
 226         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 227           return iTlbC0TsbPs1;
 228         case MISCREG_MMU_ITLB_C0_CONFIG:
 229           return iTlbC0Config;
 230         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 231           return iTlbCXTsbPs0;
 232         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 233           return iTlbCXTsbPs1;
 234         case MISCREG_MMU_ITLB_CX_CONFIG:
 235           return iTlbCXConfig;
 236         case MISCREG_MMU_ITLB_SFSR:
 237           return iTlbSfsr;
 238         case MISCREG_MMU_ITLB_TAG_ACCESS:
 239           return iTlbTagAccess;
 240
 241         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 242           return dTlbC0TsbPs0;
 243         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 244           return dTlbC0TsbPs1;
 245         case MISCREG_MMU_DTLB_C0_CONFIG:
 246           return dTlbC0Config;
 247         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 248           return dTlbCXTsbPs0;
 249         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 250           return dTlbCXTsbPs1;
 251         case MISCREG_MMU_DTLB_CX_CONFIG:
 252           return dTlbCXConfig;
 253         case MISCREG_MMU_DTLB_SFSR:
 254           return dTlbSfsr;
 255         case MISCREG_MMU_DTLB_SFAR:
 256           return dTlbSfar;
 257         case MISCREG_MMU_DTLB_TAG_ACCESS:
 258           return dTlbTagAccess;
 259
 260         case MISCREG_SCRATCHPAD_R0:
 261           return scratchPad[0];
 262         case MISCREG_SCRATCHPAD_R1:
 263           return scratchPad[1];
 264         case MISCREG_SCRATCHPAD_R2:
 265           return scratchPad[2];
 266         case MISCREG_SCRATCHPAD_R3:
 267           return scratchPad[3];
 268         case MISCREG_SCRATCHPAD_R4:
 269           return scratchPad[4];
 270         case MISCREG_SCRATCHPAD_R5:
 271           return scratchPad[5];
 272         case MISCREG_SCRATCHPAD_R6:
 273           return scratchPad[6];
 274         case MISCREG_SCRATCHPAD_R7:
 275           return scratchPad[7];
 276
 277         default:
 278           panic("Miscellaneous register %d not implemented\n", miscReg);
 279     }
 280 }
 281
 282 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 283 {
 284     switch (miscReg) {
 285         case MISCREG_TICK:
 286         case MISCREG_PRIVTICK:
 287           return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
 288               (tick & ~(mask(63))) << 63;
 289         case MISCREG_FPRS:
 290           panic("FPU not implemented\n");
 291         case MISCREG_PCR:
 292         case MISCREG_PIC:
 293           panic("Performance Instrumentation not impl\n");
 294         /** Floating Point Status Register */
 295         case MISCREG_FSR:
 296           panic("Floating Point not implemented\n");
 297 //We'll include this only in FS so we don't need the SparcSystem type around
 298 //in SE.
 299 #if FULL_SYSTEM
 300         case MISCREG_STICK:
 301           SparcSystem *sys;
 302           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 303           assert(sys != NULL);
 304           return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
 305 #endif
 306         case MISCREG_HVER:
 307           return NWindows | MaxTL << 8 | MaxGL << 16;
 308     }
 309     return readReg(miscReg);
 310 }
 311
 312 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 313 {
 314     switch (miscReg) {
 315         case MISCREG_Y:
 316           y = val;
 317           break;
 318         case MISCREG_CCR:
 319           ccr = val;
 320           break;
 321         case MISCREG_ASI:
 322           asi = val;
 323           break;
 324         case MISCREG_FPRS:
 325           fprs = val;
 326           break;
 327         case MISCREG_TICK:
 328           tick = val;
 329           break;
 330         case MISCREG_PCR:
 331           panic("PCR not implemented\n");
 332         case MISCREG_PIC:
 333           panic("PIC not implemented\n");
 334         case MISCREG_GSR:
 335           gsr = val;
 336           break;
 337         case MISCREG_SOFTINT:
 338           softint = val;
 339           break;
 340         case MISCREG_TICK_CMPR:
 341           tick_cmpr = val;
 342           break;
 343         case MISCREG_STICK:
 344           stick = val;
 345           break;
 346         case MISCREG_STICK_CMPR:
 347           stick_cmpr = val;
 348           break;
 349
 350         /** Privilged Registers */
 351         case MISCREG_TPC:
 352           tpc[tl-1] = val;
 353           break;
 354         case MISCREG_TNPC:
 355           tnpc[tl-1] = val;
 356           break;
 357         case MISCREG_TSTATE:
 358           tstate[tl-1] = val;
 359           break;
 360         case MISCREG_TT:
 361           tt[tl-1] = val;
 362           break;
 363         case MISCREG_PRIVTICK:
 364           panic("Priviliged access to tick regesiters not implemented\n");
 365         case MISCREG_TBA:
 366           // clear lower 7 bits on writes.
 367           tba = val & ULL(~0x7FFF);
 368           break;
 369         case MISCREG_PSTATE:
 370           pstate = (val & PSTATE_MASK);
 371           break;
 372         case MISCREG_TL:
 373           tl = val;
 374           break;
 375         case MISCREG_PIL:
 376           pil = val;
 377           break;
 378         case MISCREG_CWP:
 379           cwp = val;
 380           break;
 381         case MISCREG_CANSAVE:
 382           cansave = val;
 383           break;
 384         case MISCREG_CANRESTORE:
 385           canrestore = val;
 386           break;
 387         case MISCREG_CLEANWIN:
 388           cleanwin = val;
 389           break;
 390         case MISCREG_OTHERWIN:
 391           otherwin = val;
 392           break;
 393         case MISCREG_WSTATE:
 394           wstate = val;
 395           break;
 396         case MISCREG_GL:
 397           gl = val;
 398           break;
 399
 400         /** Hyper privileged registers */
 401         case MISCREG_HPSTATE:
 402           hpstate = val;
 403           break;
 404         case MISCREG_HTSTATE:
 405           htstate[tl-1] = val;
 406           break;
 407         case MISCREG_HINTP:
 408           panic("HINTP not implemented\n");
 409         case MISCREG_HTBA:
 410           htba = val;
 411           break;
 412         case MISCREG_STRAND_STS_REG:
 413           strandStatusReg = val;
 414           break;
 415         case MISCREG_HSTICK_CMPR:
 416           hstick_cmpr = val;
 417           break;
 418
 419         /** Floating Point Status Register */
 420         case MISCREG_FSR:
 421           fsr = val;
 422           break;
 423
 424         case MISCREG_MMU_P_CONTEXT:
 425           priContext = val;
 426           break;
 427         case MISCREG_MMU_S_CONTEXT:
 428           secContext = val;
 429           break;
 430         case MISCREG_MMU_PART_ID:
 431           partId = val;
 432           break;
 433         case MISCREG_MMU_LSU_CTRL:
 434           lsuCtrlReg = val;
 435           break;
 436
 437         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 438           iTlbC0TsbPs0 = val;
 439           break;
 440         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 441           iTlbC0TsbPs1 = val;
 442           break;
 443         case MISCREG_MMU_ITLB_C0_CONFIG:
 444           iTlbC0Config = val;
 445           break;
 446         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 447           iTlbCXTsbPs0 = val;
 448           break;
 449         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 450           iTlbCXTsbPs1 = val;
 451           break;
 452         case MISCREG_MMU_ITLB_CX_CONFIG:
 453           iTlbCXConfig = val;
 454           break;
 455         case MISCREG_MMU_ITLB_SFSR:
 456           iTlbSfsr = val;
 457           break;
 458         case MISCREG_MMU_ITLB_TAG_ACCESS:
 459           iTlbTagAccess = val;
 460           break;
 461
 462         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 463           dTlbC0TsbPs0 = val;
 464           break;
 465         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 466           dTlbC0TsbPs1 = val;
 467           break;
 468         case MISCREG_MMU_DTLB_C0_CONFIG:
 469           dTlbC0Config = val;
 470           break;
 471         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 472           dTlbCXTsbPs0 = val;
 473           break;
 474         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 475           dTlbCXTsbPs1 = val;
 476           break;
 477         case MISCREG_MMU_DTLB_CX_CONFIG:
 478           dTlbCXConfig = val;
 479           break;
 480         case MISCREG_MMU_DTLB_SFSR:
 481           dTlbSfsr = val;
 482           break;
 483         case MISCREG_MMU_DTLB_SFAR:
 484           dTlbSfar = val;
 485           break;
 486         case MISCREG_MMU_DTLB_TAG_ACCESS:
 487           dTlbTagAccess = val;
 488           break;
 489
 490         case MISCREG_SCRATCHPAD_R0:
 491            scratchPad[0] = val;
 492         case MISCREG_SCRATCHPAD_R1:
 493            scratchPad[1] = val;
 494         case MISCREG_SCRATCHPAD_R2:
 495            scratchPad[2] = val;
 496         case MISCREG_SCRATCHPAD_R3:
 497            scratchPad[3] = val;
 498         case MISCREG_SCRATCHPAD_R4:
 499            scratchPad[4] = val;
 500         case MISCREG_SCRATCHPAD_R5:
 501            scratchPad[5] = val;
 502         case MISCREG_SCRATCHPAD_R6:
 503            scratchPad[6] = val;
 504         case MISCREG_SCRATCHPAD_R7:
 505            scratchPad[7] = val;
 506
 507         default:
 508           panic("Miscellaneous register %d not implemented\n", miscReg);
 509     }
 510 }
 511
 512 void MiscRegFile::setRegWithEffect(int miscReg,
 513         const MiscReg &val, ThreadContext * tc)
 514 {
 515     const uint64_t Bit64 = (1ULL << 63);
 516 #if FULL_SYSTEM
 517     uint64_t time;
 518     SparcSystem *sys;
 519 #endif
 520     switch (miscReg) {
 521         case MISCREG_TICK:
 522           tick = tc->getCpuPtr()->curCycle() - val  & ~Bit64;
 523           tick |= val & Bit64;
 524           break;
 525         case MISCREG_FPRS:
 526           //Configure the fpu based on the fprs
 527           break;
 528         case MISCREG_PCR:
 529           //Set up performance counting based on pcr value
 530           break;
 531         case MISCREG_PSTATE:
 532           pstate = val & PSTATE_MASK;
 533           return;
 534         case MISCREG_TL:
 535           tl = val;
 536           return;
 537         case MISCREG_CWP:
 538           tc->changeRegFileContext(CONTEXT_CWP, val);
 539           break;
 540         case MISCREG_GL:
 541           tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 542           break;
 543         case MISCREG_SOFTINT:
 544           //We need to inject interrupts, and or notify the interrupt
 545           //object that it needs to use a different interrupt level.
 546           //Any newly appropriate interrupts will happen when the cpu gets
 547           //around to checking for them. This might not be quite what we
 548           //want.
 549           break;
 550         case MISCREG_SOFTINT_CLR:
 551           //Do whatever this is supposed to do...
 552           break;
 553         case MISCREG_SOFTINT_SET:
 554           //Do whatever this is supposed to do...
 555           break;
 556 #if FULL_SYSTEM
 557         case MISCREG_TICK_CMPR:
 558           if (tickCompare == NULL)
 559               tickCompare = new TickCompareEvent(this, tc);
 560           setReg(miscReg, val);
 561           if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
 562                   tickCompare->deschedule();
 563           time = (tick_cmpr & mask(63)) - (tick & mask(63));
 564           if (!(tick_cmpr & ~mask(63)) && time > 0)
 565               tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
 566           break;
 567 #endif
 568         case MISCREG_PIL:
 569           //We need to inject interrupts, and or notify the interrupt
 570           //object that it needs to use a different interrupt level.
 571           //Any newly appropriate interrupts will happen when the cpu gets
 572           //around to checking for them. This might not be quite what we
 573           //want.
 574           break;
 575 //We'll include this only in FS so we don't need the SparcSystem type around
 576 //in SE.
 577 #if FULL_SYSTEM
 578         case MISCREG_STICK:
 579           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 580           assert(sys != NULL);
 581           sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
 582           stick |= val & Bit64;
 583           break;
 584         case MISCREG_STICK_CMPR:
 585           if (sTickCompare == NULL)
 586               sTickCompare = new STickCompareEvent(this, tc);
 587           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 588           assert(sys != NULL);
 589           if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
 590                   sTickCompare->deschedule();
 591           time = (stick_cmpr & mask(63)) - sys->sysTick;
 592           if (!(stick_cmpr & ~mask(63)) && time > 0)
 593               sTickCompare->schedule(time * Clock::Int::ns);
 594           break;
 595         case MISCREG_HSTICK_CMPR:
 596           if (hSTickCompare == NULL)
 597               hSTickCompare = new HSTickCompareEvent(this, tc);
 598           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 599           assert(sys != NULL);
 600           if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
 601                   hSTickCompare->deschedule();
 602           int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
 603           if (!(hstick_cmpr & ~mask(63)) && time > 0)
 604               hSTickCompare->schedule(time * Clock::Int::ns);
 605           break;
 606 #endif
 607     }
 608     setReg(miscReg, val);
 609 }
 610
 611 void MiscRegFile::serialize(std::ostream & os)
 612 {
 613     SERIALIZE_SCALAR(pstate);
 614     SERIALIZE_SCALAR(tba);
 615     SERIALIZE_SCALAR(y);
 616     SERIALIZE_SCALAR(pil);
 617     SERIALIZE_SCALAR(gl);
 618     SERIALIZE_SCALAR(cwp);
 619     SERIALIZE_ARRAY(tt, MaxTL);
 620     SERIALIZE_SCALAR(ccr);
 621     SERIALIZE_SCALAR(asi);
 622     SERIALIZE_SCALAR(tl);
 623     SERIALIZE_ARRAY(tpc, MaxTL);
 624     SERIALIZE_ARRAY(tnpc, MaxTL);
 625     SERIALIZE_ARRAY(tstate, MaxTL);
 626     SERIALIZE_SCALAR(tick);
 627     SERIALIZE_SCALAR(cansave);
 628     SERIALIZE_SCALAR(canrestore);
 629     SERIALIZE_SCALAR(otherwin);
 630     SERIALIZE_SCALAR(cleanwin);
 631     SERIALIZE_SCALAR(wstate);
 632     SERIALIZE_SCALAR(fsr);
 633     SERIALIZE_SCALAR(fprs);
 634     SERIALIZE_SCALAR(hpstate);
 635     SERIALIZE_ARRAY(htstate, MaxTL);
 636     SERIALIZE_SCALAR(htba);
 637     SERIALIZE_SCALAR(hstick_cmpr);
 638     SERIALIZE_SCALAR(strandStatusReg);
 639     SERIALIZE_SCALAR(priContext);
 640     SERIALIZE_SCALAR(secContext);
 641     SERIALIZE_SCALAR(partId);
 642     SERIALIZE_SCALAR(lsuCtrlReg);
 643     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 644     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 645     SERIALIZE_SCALAR(iTlbC0Config);
 646     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 647     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 648     SERIALIZE_SCALAR(iTlbCXConfig);
 649     SERIALIZE_SCALAR(iTlbSfsr);
 650     SERIALIZE_SCALAR(iTlbTagAccess);
 651     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 652     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 653     SERIALIZE_SCALAR(dTlbC0Config);
 654     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 655     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 656     SERIALIZE_SCALAR(dTlbSfsr);
 657     SERIALIZE_SCALAR(dTlbSfar);
 658     SERIALIZE_SCALAR(dTlbTagAccess);
 659     SERIALIZE_ARRAY(scratchPad,8);
 660 }
 661
 662 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 663 {
 664     UNSERIALIZE_SCALAR(pstate);
 665     UNSERIALIZE_SCALAR(tba);
 666     UNSERIALIZE_SCALAR(y);
 667     UNSERIALIZE_SCALAR(pil);
 668     UNSERIALIZE_SCALAR(gl);
 669     UNSERIALIZE_SCALAR(cwp);
 670     UNSERIALIZE_ARRAY(tt, MaxTL);
 671     UNSERIALIZE_SCALAR(ccr);
 672     UNSERIALIZE_SCALAR(asi);
 673     UNSERIALIZE_SCALAR(tl);
 674     UNSERIALIZE_ARRAY(tpc, MaxTL);
 675     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 676     UNSERIALIZE_ARRAY(tstate, MaxTL);
 677     UNSERIALIZE_SCALAR(tick);
 678     UNSERIALIZE_SCALAR(cansave);
 679     UNSERIALIZE_SCALAR(canrestore);
 680     UNSERIALIZE_SCALAR(otherwin);
 681     UNSERIALIZE_SCALAR(cleanwin);
 682     UNSERIALIZE_SCALAR(wstate);
 683     UNSERIALIZE_SCALAR(fsr);
 684     UNSERIALIZE_SCALAR(fprs);
 685     UNSERIALIZE_SCALAR(hpstate);
 686     UNSERIALIZE_ARRAY(htstate, MaxTL);
 687     UNSERIALIZE_SCALAR(htba);
 688     UNSERIALIZE_SCALAR(hstick_cmpr);
 689     UNSERIALIZE_SCALAR(strandStatusReg);
 690     UNSERIALIZE_SCALAR(priContext);
 691     UNSERIALIZE_SCALAR(secContext);
 692     UNSERIALIZE_SCALAR(partId);
 693     UNSERIALIZE_SCALAR(lsuCtrlReg);
 694     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 695     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 696     UNSERIALIZE_SCALAR(iTlbC0Config);
 697     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 698     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 699     UNSERIALIZE_SCALAR(iTlbCXConfig);
 700     UNSERIALIZE_SCALAR(iTlbSfsr);
 701     UNSERIALIZE_SCALAR(iTlbTagAccess);
 702     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 703     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 704     UNSERIALIZE_SCALAR(dTlbC0Config);
 705     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 706     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 707     UNSERIALIZE_SCALAR(dTlbSfsr);
 708     UNSERIALIZE_SCALAR(dTlbSfar);
 709     UNSERIALIZE_SCALAR(dTlbTagAccess);
 710     UNSERIALIZE_ARRAY(scratchPad,8);}
 711
 712 #if FULL_SYSTEM
 713 void
 714 MiscRegFile::processTickCompare(ThreadContext *tc)
 715 {
 716     panic("tick compare not implemented\n");
 717 }
 718
 719 void
 720 MiscRegFile::processSTickCompare(ThreadContext *tc)
 721 {
 722     panic("tick compare not implemented\n");
 723 }
 724
 725 void
 726 MiscRegFile::processHSTickCompare(ThreadContext *tc)
 727 {
 728     panic("tick compare not implemented\n");
 729 }
 730 #endif