src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 #if FULL_SYSTEM
  41 #include "arch/sparc/system.hh"
  42 #endif
  43
  44 using namespace SparcISA;
  45 using namespace std;
  46
  47 class Checkpoint;
  48
  49 //These functions map register indices to names
  50 string SparcISA::getMiscRegName(RegIndex index)
  51 {
  52     static::string miscRegName[NumMiscRegs] =
  53         {"y", "ccr", "asi", "tick", "pc", "fprs", "pcr", "pic",
  54          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  55          "stick", "stick_cmpr",
  56          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  57          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  58          "wstate", "gl",
  59          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  60          "hstick_cmpr",
  61          "fsr"};
  62     return miscRegName[index];
  63 }
  64
  65 void MiscRegFile::reset()
  66 {
  67     y = 0;
  68     ccr = 0;
  69     asi = 0;
  70     tick = 0;
  71     fprs = 0;
  72     gsr = 0;
  73     softint = 0;
  74     tick_cmpr = 0;
  75     stick = 0;
  76     stick_cmpr = 0;
  77     memset(tpc, 0, sizeof(tpc));
  78     memset(tnpc, 0, sizeof(tnpc));
  79     memset(tstate, 0, sizeof(tstate));
  80     memset(tt, 0, sizeof(tt));
  81     pstate = 0;
  82     tl = 0;
  83     pil = 0;
  84     cwp = 0;
  85     cansave = 0;
  86     canrestore = 0;
  87     cleanwin = 0;
  88     otherwin = 0;
  89     wstate = 0;
  90     gl = 0;
  91     hpstate = 0;
  92     memset(htstate, 0, sizeof(htstate));
  93     hintp = 0;
  94     htba = 0;
  95     hstick_cmpr = 0;
  96     strandStatusReg = 0;
  97     fsr = 0;
  98
  99     priContext = 0;
 100     secContext = 0;
 101     partId = 0;
 102     lsuCtrlReg = 0;
 103
 104     iTlbC0TsbPs0 = 0;
 105     iTlbC0TsbPs1 = 0;
 106     iTlbC0Config = 0;
 107     iTlbCXTsbPs0 = 0;
 108     iTlbCXTsbPs1 = 0;
 109     iTlbCXConfig = 0;
 110     iTlbSfsr = 0;
 111     iTlbTagAccess = 0;
 112
 113     dTlbC0TsbPs0 = 0;
 114     dTlbC0TsbPs1 = 0;
 115     dTlbC0Config = 0;
 116     dTlbCXTsbPs0 = 0;
 117     dTlbCXTsbPs1 = 0;
 118     dTlbCXConfig = 0;
 119     dTlbSfsr = 0;
 120     dTlbSfar = 0;
 121     dTlbTagAccess = 0;
 122
 123     memset(scratchPad, 0, sizeof(scratchPad));
 124 }
 125
 126 MiscReg MiscRegFile::readReg(int miscReg)
 127 {
 128     switch (miscReg) {
 129         case MISCREG_Y:
 130           return y;
 131         case MISCREG_CCR:
 132           return ccr;
 133         case MISCREG_ASI:
 134           return asi;
 135         case MISCREG_FPRS:
 136           return fprs;
 137         case MISCREG_TICK:
 138            return tick;
 139         case MISCREG_PCR:
 140           panic("PCR not implemented\n");
 141         case MISCREG_PIC:
 142           panic("PIC not implemented\n");
 143         case MISCREG_GSR:
 144           return gsr;
 145         case MISCREG_SOFTINT:
 146            return softint;
 147         case MISCREG_TICK_CMPR:
 148            return tick_cmpr;
 149         case MISCREG_STICK:
 150            return stick;
 151         case MISCREG_STICK_CMPR:
 152            return stick_cmpr;
 153
 154         /** Privilged Registers */
 155         case MISCREG_TPC:
 156           return tpc[tl-1];
 157         case MISCREG_TNPC:
 158           return tnpc[tl-1];
 159         case MISCREG_TSTATE:
 160           return tstate[tl-1];
 161         case MISCREG_TT:
 162           return tt[tl-1];
 163         case MISCREG_PRIVTICK:
 164           panic("Priviliged access to tick registers not implemented\n");
 165         case MISCREG_TBA:
 166           return tba;
 167         case MISCREG_PSTATE:
 168           return pstate;
 169         case MISCREG_TL:
 170           return tl;
 171         case MISCREG_PIL:
 172           return pil;
 173         case MISCREG_CWP:
 174           return cwp;
 175         case MISCREG_CANSAVE:
 176           return cansave;
 177         case MISCREG_CANRESTORE:
 178           return canrestore;
 179         case MISCREG_CLEANWIN:
 180           return cleanwin;
 181         case MISCREG_OTHERWIN:
 182           return otherwin;
 183         case MISCREG_WSTATE:
 184           return wstate;
 185         case MISCREG_GL:
 186           return gl;
 187
 188         /** Hyper privileged registers */
 189         case MISCREG_HPSTATE:
 190           return hpstate;
 191         case MISCREG_HTSTATE:
 192           return htstate[tl-1];
 193         case MISCREG_HINTP:
 194           panic("HINTP not implemented\n");
 195         case MISCREG_HTBA:
 196           return htba;
 197         case MISCREG_HVER:
 198           return NWindows | MaxTL << 8 | MaxGL << 16;
 199         case MISCREG_STRAND_STS_REG:
 200           return strandStatusReg;
 201         case MISCREG_HSTICK_CMPR:
 202           return hstick_cmpr;
 203
 204         /** Floating Point Status Register */
 205         case MISCREG_FSR:
 206           return fsr;
 207
 208         case MISCREG_MMU_P_CONTEXT:
 209           return priContext;
 210         case MISCREG_MMU_S_CONTEXT:
 211           return secContext;
 212         case MISCREG_MMU_PART_ID:
 213           return partId;
 214         case MISCREG_MMU_LSU_CTRL:
 215           return lsuCtrlReg;
 216
 217         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 218           return iTlbC0TsbPs0;
 219         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 220           return iTlbC0TsbPs1;
 221         case MISCREG_MMU_ITLB_C0_CONFIG:
 222           return iTlbC0Config;
 223         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 224           return iTlbCXTsbPs0;
 225         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 226           return iTlbCXTsbPs1;
 227         case MISCREG_MMU_ITLB_CX_CONFIG:
 228           return iTlbCXConfig;
 229         case MISCREG_MMU_ITLB_SFSR:
 230           return iTlbSfsr;
 231         case MISCREG_MMU_ITLB_TAG_ACCESS:
 232           return iTlbTagAccess;
 233
 234         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 235           return dTlbC0TsbPs0;
 236         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 237           return dTlbC0TsbPs1;
 238         case MISCREG_MMU_DTLB_C0_CONFIG:
 239           return dTlbC0Config;
 240         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 241           return dTlbCXTsbPs0;
 242         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 243           return dTlbCXTsbPs1;
 244         case MISCREG_MMU_DTLB_CX_CONFIG:
 245           return dTlbCXConfig;
 246         case MISCREG_MMU_DTLB_SFSR:
 247           return dTlbSfsr;
 248         case MISCREG_MMU_DTLB_SFAR:
 249           return dTlbSfar;
 250         case MISCREG_MMU_DTLB_TAG_ACCESS:
 251           return dTlbTagAccess;
 252
 253         case MISCREG_SCRATCHPAD_R0:
 254           return scratchPad[0];
 255         case MISCREG_SCRATCHPAD_R1:
 256           return scratchPad[1];
 257         case MISCREG_SCRATCHPAD_R2:
 258           return scratchPad[2];
 259         case MISCREG_SCRATCHPAD_R3:
 260           return scratchPad[3];
 261         case MISCREG_SCRATCHPAD_R4:
 262           return scratchPad[4];
 263         case MISCREG_SCRATCHPAD_R5:
 264           return scratchPad[5];
 265         case MISCREG_SCRATCHPAD_R6:
 266           return scratchPad[6];
 267         case MISCREG_SCRATCHPAD_R7:
 268           return scratchPad[7];
 269
 270         default:
 271           panic("Miscellaneous register %d not implemented\n", miscReg);
 272     }
 273 }
 274
 275 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 276 {
 277     switch (miscReg) {
 278         case MISCREG_TICK:
 279         case MISCREG_PRIVTICK:
 280           return tc->getCpuPtr()->curCycle() - (tick & mask(63)) |
 281               (tick & ~(mask(63))) << 63;
 282         case MISCREG_FPRS:
 283           panic("FPU not implemented\n");
 284         case MISCREG_PCR:
 285         case MISCREG_PIC:
 286           panic("Performance Instrumentation not impl\n");
 287         /** Floating Point Status Register */
 288         case MISCREG_FSR:
 289           panic("Floating Point not implemented\n");
 290 //We'll include this only in FS so we don't need the SparcSystem type around
 291 //in SE.
 292 #if FULL_SYSTEM
 293         case MISCREG_STICK:
 294           SparcSystem *sys;
 295           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 296           assert(sys != NULL);
 297           return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
 298 #endif
 299         case MISCREG_HVER:
 300           return NWindows | MaxTL << 8 | MaxGL << 16;
 301     }
 302     return readReg(miscReg);
 303 }
 304
 305 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 306 {
 307     switch (miscReg) {
 308         case MISCREG_Y:
 309           y = val;
 310           break;
 311         case MISCREG_CCR:
 312           ccr = val;
 313           break;
 314         case MISCREG_ASI:
 315           asi = val;
 316           break;
 317         case MISCREG_FPRS:
 318           fprs = val;
 319           break;
 320         case MISCREG_TICK:
 321           tick = val;
 322           break;
 323         case MISCREG_PCR:
 324           panic("PCR not implemented\n");
 325         case MISCREG_PIC:
 326           panic("PIC not implemented\n");
 327         case MISCREG_GSR:
 328           gsr = val;
 329           break;
 330         case MISCREG_SOFTINT:
 331           softint = val;
 332           break;
 333         case MISCREG_TICK_CMPR:
 334           tick_cmpr = val;
 335           break;
 336         case MISCREG_STICK:
 337           stick = val;
 338           break;
 339         case MISCREG_STICK_CMPR:
 340           stick_cmpr = val;
 341           break;
 342
 343         /** Privilged Registers */
 344         case MISCREG_TPC:
 345           tpc[tl-1] = val;
 346           break;
 347         case MISCREG_TNPC:
 348           tnpc[tl-1] = val;
 349           break;
 350         case MISCREG_TSTATE:
 351           tstate[tl-1] = val;
 352           break;
 353         case MISCREG_TT:
 354           tt[tl-1] = val;
 355           break;
 356         case MISCREG_PRIVTICK:
 357           panic("Priviliged access to tick regesiters not implemented\n");
 358         case MISCREG_TBA:
 359           // clear lower 7 bits on writes.
 360           tba = val & ULL(~0x7FFF);
 361           break;
 362         case MISCREG_PSTATE:
 363           pstate = val;
 364           break;
 365         case MISCREG_TL:
 366           tl = val;
 367           break;
 368         case MISCREG_PIL:
 369           pil = val;
 370           break;
 371         case MISCREG_CWP:
 372           cwp = val;
 373           break;
 374         case MISCREG_CANSAVE:
 375           cansave = val;
 376           break;
 377         case MISCREG_CANRESTORE:
 378           canrestore = val;
 379           break;
 380         case MISCREG_CLEANWIN:
 381           cleanwin = val;
 382           break;
 383         case MISCREG_OTHERWIN:
 384           otherwin = val;
 385           break;
 386         case MISCREG_WSTATE:
 387           wstate = val;
 388           break;
 389         case MISCREG_GL:
 390           gl = val;
 391           break;
 392
 393         /** Hyper privileged registers */
 394         case MISCREG_HPSTATE:
 395           hpstate = val;
 396           break;
 397         case MISCREG_HTSTATE:
 398           htstate[tl-1] = val;
 399           break;
 400         case MISCREG_HINTP:
 401           panic("HINTP not implemented\n");
 402         case MISCREG_HTBA:
 403           htba = val;
 404           break;
 405         case MISCREG_STRAND_STS_REG:
 406           strandStatusReg = val;
 407           break;
 408         case MISCREG_HSTICK_CMPR:
 409           hstick_cmpr = val;
 410           break;
 411
 412         /** Floating Point Status Register */
 413         case MISCREG_FSR:
 414           fsr = val;
 415           break;
 416
 417         case MISCREG_MMU_P_CONTEXT:
 418           priContext = val;
 419           break;
 420         case MISCREG_MMU_S_CONTEXT:
 421           secContext = val;
 422           break;
 423         case MISCREG_MMU_PART_ID:
 424           partId = val;
 425           break;
 426         case MISCREG_MMU_LSU_CTRL:
 427           lsuCtrlReg = val;
 428           break;
 429
 430         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 431           iTlbC0TsbPs0 = val;
 432           break;
 433         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 434           iTlbC0TsbPs1 = val;
 435           break;
 436         case MISCREG_MMU_ITLB_C0_CONFIG:
 437           iTlbC0Config = val;
 438           break;
 439         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 440           iTlbCXTsbPs0 = val;
 441           break;
 442         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 443           iTlbCXTsbPs1 = val;
 444           break;
 445         case MISCREG_MMU_ITLB_CX_CONFIG:
 446           iTlbCXConfig = val;
 447           break;
 448         case MISCREG_MMU_ITLB_SFSR:
 449           iTlbSfsr = val;
 450           break;
 451         case MISCREG_MMU_ITLB_TAG_ACCESS:
 452           iTlbTagAccess = val;
 453           break;
 454
 455         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 456           dTlbC0TsbPs0 = val;
 457           break;
 458         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 459           dTlbC0TsbPs1 = val;
 460           break;
 461         case MISCREG_MMU_DTLB_C0_CONFIG:
 462           dTlbC0Config = val;
 463           break;
 464         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 465           dTlbCXTsbPs0 = val;
 466           break;
 467         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 468           dTlbCXTsbPs1 = val;
 469           break;
 470         case MISCREG_MMU_DTLB_CX_CONFIG:
 471           dTlbCXConfig = val;
 472           break;
 473         case MISCREG_MMU_DTLB_SFSR:
 474           dTlbSfsr = val;
 475           break;
 476         case MISCREG_MMU_DTLB_SFAR:
 477           dTlbSfar = val;
 478           break;
 479         case MISCREG_MMU_DTLB_TAG_ACCESS:
 480           dTlbTagAccess = val;
 481           break;
 482
 483         case MISCREG_SCRATCHPAD_R0:
 484            scratchPad[0] = val;
 485         case MISCREG_SCRATCHPAD_R1:
 486            scratchPad[1] = val;
 487         case MISCREG_SCRATCHPAD_R2:
 488            scratchPad[2] = val;
 489         case MISCREG_SCRATCHPAD_R3:
 490            scratchPad[3] = val;
 491         case MISCREG_SCRATCHPAD_R4:
 492            scratchPad[4] = val;
 493         case MISCREG_SCRATCHPAD_R5:
 494            scratchPad[5] = val;
 495         case MISCREG_SCRATCHPAD_R6:
 496            scratchPad[6] = val;
 497         case MISCREG_SCRATCHPAD_R7:
 498            scratchPad[7] = val;
 499
 500         default:
 501           panic("Miscellaneous register %d not implemented\n", miscReg);
 502     }
 503 }
 504
 505 void MiscRegFile::setRegWithEffect(int miscReg,
 506         const MiscReg &val, ThreadContext * tc)
 507 {
 508     const uint64_t Bit64 = (1ULL << 63);
 509 #if FULL_SYSTEM
 510     uint64_t time;
 511     SparcSystem *sys;
 512 #endif
 513     switch (miscReg) {
 514         case MISCREG_TICK:
 515           tick = tc->getCpuPtr()->curCycle() - val  & ~Bit64;
 516           tick |= val & Bit64;
 517           break;
 518         case MISCREG_FPRS:
 519           //Configure the fpu based on the fprs
 520           break;
 521         case MISCREG_PCR:
 522           //Set up performance counting based on pcr value
 523           break;
 524         case MISCREG_PSTATE:
 525           pstate = val;
 526           return;
 527         case MISCREG_TL:
 528           tl = val;
 529           return;
 530         case MISCREG_CWP:
 531           tc->changeRegFileContext(CONTEXT_CWP, val);
 532           break;
 533         case MISCREG_GL:
 534           tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 535           break;
 536         case MISCREG_SOFTINT:
 537           //We need to inject interrupts, and or notify the interrupt
 538           //object that it needs to use a different interrupt level.
 539           //Any newly appropriate interrupts will happen when the cpu gets
 540           //around to checking for them. This might not be quite what we
 541           //want.
 542           break;
 543         case MISCREG_SOFTINT_CLR:
 544           //Do whatever this is supposed to do...
 545           break;
 546         case MISCREG_SOFTINT_SET:
 547           //Do whatever this is supposed to do...
 548           break;
 549 #if FULL_SYSTEM
 550         case MISCREG_TICK_CMPR:
 551           if (tickCompare == NULL)
 552               tickCompare = new TickCompareEvent(this, tc);
 553           setReg(miscReg, val);
 554           if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
 555                   tickCompare->deschedule();
 556           time = (tick_cmpr & mask(63)) - (tick & mask(63));
 557           if (!(tick_cmpr & ~mask(63)) && time > 0)
 558               tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
 559           break;
 560 #endif
 561         case MISCREG_PIL:
 562           //We need to inject interrupts, and or notify the interrupt
 563           //object that it needs to use a different interrupt level.
 564           //Any newly appropriate interrupts will happen when the cpu gets
 565           //around to checking for them. This might not be quite what we
 566           //want.
 567           break;
 568 //We'll include this only in FS so we don't need the SparcSystem type around
 569 //in SE.
 570 #if FULL_SYSTEM
 571         case MISCREG_STICK:
 572           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 573           assert(sys != NULL);
 574           sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
 575           stick |= val & Bit64;
 576           break;
 577         case MISCREG_STICK_CMPR:
 578           if (sTickCompare == NULL)
 579               sTickCompare = new STickCompareEvent(this, tc);
 580           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 581           assert(sys != NULL);
 582           if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
 583                   sTickCompare->deschedule();
 584           time = (stick_cmpr & mask(63)) - sys->sysTick;
 585           if (!(stick_cmpr & ~mask(63)) && time > 0)
 586               sTickCompare->schedule(time * Clock::Int::ns);
 587           break;
 588         case MISCREG_HSTICK_CMPR:
 589           if (hSTickCompare == NULL)
 590               hSTickCompare = new HSTickCompareEvent(this, tc);
 591           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 592           assert(sys != NULL);
 593           if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
 594                   hSTickCompare->deschedule();
 595           int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
 596           if (!(hstick_cmpr & ~mask(63)) && time > 0)
 597               hSTickCompare->schedule(time * Clock::Int::ns);
 598           break;
 599 #endif
 600     }
 601     setReg(miscReg, val);
 602 }
 603
 604 void MiscRegFile::serialize(std::ostream & os)
 605 {
 606     SERIALIZE_SCALAR(pstate);
 607     SERIALIZE_SCALAR(tba);
 608     SERIALIZE_SCALAR(y);
 609     SERIALIZE_SCALAR(pil);
 610     SERIALIZE_SCALAR(gl);
 611     SERIALIZE_SCALAR(cwp);
 612     SERIALIZE_ARRAY(tt, MaxTL);
 613     SERIALIZE_SCALAR(ccr);
 614     SERIALIZE_SCALAR(asi);
 615     SERIALIZE_SCALAR(tl);
 616     SERIALIZE_ARRAY(tpc, MaxTL);
 617     SERIALIZE_ARRAY(tnpc, MaxTL);
 618     SERIALIZE_ARRAY(tstate, MaxTL);
 619     SERIALIZE_SCALAR(tick);
 620     SERIALIZE_SCALAR(cansave);
 621     SERIALIZE_SCALAR(canrestore);
 622     SERIALIZE_SCALAR(otherwin);
 623     SERIALIZE_SCALAR(cleanwin);
 624     SERIALIZE_SCALAR(wstate);
 625     SERIALIZE_SCALAR(fsr);
 626     SERIALIZE_SCALAR(fprs);
 627     SERIALIZE_SCALAR(hpstate);
 628     SERIALIZE_ARRAY(htstate, MaxTL);
 629     SERIALIZE_SCALAR(htba);
 630     SERIALIZE_SCALAR(hstick_cmpr);
 631     SERIALIZE_SCALAR(strandStatusReg);
 632     SERIALIZE_SCALAR(priContext);
 633     SERIALIZE_SCALAR(secContext);
 634     SERIALIZE_SCALAR(partId);
 635     SERIALIZE_SCALAR(lsuCtrlReg);
 636     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 637     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 638     SERIALIZE_SCALAR(iTlbC0Config);
 639     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 640     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 641     SERIALIZE_SCALAR(iTlbCXConfig);
 642     SERIALIZE_SCALAR(iTlbSfsr);
 643     SERIALIZE_SCALAR(iTlbTagAccess);
 644     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 645     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 646     SERIALIZE_SCALAR(dTlbC0Config);
 647     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 648     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 649     SERIALIZE_SCALAR(dTlbSfsr);
 650     SERIALIZE_SCALAR(dTlbSfar);
 651     SERIALIZE_SCALAR(dTlbTagAccess);
 652     SERIALIZE_ARRAY(scratchPad,8);
 653 }
 654
 655 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 656 {
 657     UNSERIALIZE_SCALAR(pstate);
 658     UNSERIALIZE_SCALAR(tba);
 659     UNSERIALIZE_SCALAR(y);
 660     UNSERIALIZE_SCALAR(pil);
 661     UNSERIALIZE_SCALAR(gl);
 662     UNSERIALIZE_SCALAR(cwp);
 663     UNSERIALIZE_ARRAY(tt, MaxTL);
 664     UNSERIALIZE_SCALAR(ccr);
 665     UNSERIALIZE_SCALAR(asi);
 666     UNSERIALIZE_SCALAR(tl);
 667     UNSERIALIZE_ARRAY(tpc, MaxTL);
 668     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 669     UNSERIALIZE_ARRAY(tstate, MaxTL);
 670     UNSERIALIZE_SCALAR(tick);
 671     UNSERIALIZE_SCALAR(cansave);
 672     UNSERIALIZE_SCALAR(canrestore);
 673     UNSERIALIZE_SCALAR(otherwin);
 674     UNSERIALIZE_SCALAR(cleanwin);
 675     UNSERIALIZE_SCALAR(wstate);
 676     UNSERIALIZE_SCALAR(fsr);
 677     UNSERIALIZE_SCALAR(fprs);
 678     UNSERIALIZE_SCALAR(hpstate);
 679     UNSERIALIZE_ARRAY(htstate, MaxTL);
 680     UNSERIALIZE_SCALAR(htba);
 681     UNSERIALIZE_SCALAR(hstick_cmpr);
 682     UNSERIALIZE_SCALAR(strandStatusReg);
 683     UNSERIALIZE_SCALAR(priContext);
 684     UNSERIALIZE_SCALAR(secContext);
 685     UNSERIALIZE_SCALAR(partId);
 686     UNSERIALIZE_SCALAR(lsuCtrlReg);
 687     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 688     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 689     UNSERIALIZE_SCALAR(iTlbC0Config);
 690     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 691     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 692     UNSERIALIZE_SCALAR(iTlbCXConfig);
 693     UNSERIALIZE_SCALAR(iTlbSfsr);
 694     UNSERIALIZE_SCALAR(iTlbTagAccess);
 695     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 696     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 697     UNSERIALIZE_SCALAR(dTlbC0Config);
 698     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 699     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 700     UNSERIALIZE_SCALAR(dTlbSfsr);
 701     UNSERIALIZE_SCALAR(dTlbSfar);
 702     UNSERIALIZE_SCALAR(dTlbTagAccess);
 703     UNSERIALIZE_ARRAY(scratchPad,8);}
 704
 705 #if FULL_SYSTEM
 706 void
 707 MiscRegFile::processTickCompare(ThreadContext *tc)
 708 {
 709     panic("tick compare not implemented\n");
 710 }
 711
 712 void
 713 MiscRegFile::processSTickCompare(ThreadContext *tc)
 714 {
 715     panic("tick compare not implemented\n");
 716 }
 717
 718 void
 719 MiscRegFile::processHSTickCompare(ThreadContext *tc)
 720 {
 721     panic("tick compare not implemented\n");
 722 }
 723 #endif