src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  50          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51          "stick", "stick_cmpr",
  52          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
  54          "wstate",*/ "gl",
  55          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56          "hstick_cmpr",
  57          "fsr"};
  58
  59     return miscRegName[index];
  60 }
  61
  62 enum RegMask
  63 {
  64         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  65 };
  66
  67 void MiscRegFile::clear()
  68 {
  69     //y = 0;
  70     //ccr = 0;
  71     asi = 0;
  72     tick = ULL(1) << 63;
  73     fprs = 0;
  74     gsr = 0;
  75     softint = 0;
  76     tick_cmpr = 0;
  77     stick = 0;
  78     stick_cmpr = 0;
  79     memset(tpc, 0, sizeof(tpc));
  80     memset(tnpc, 0, sizeof(tnpc));
  81     memset(tstate, 0, sizeof(tstate));
  82     memset(tt, 0, sizeof(tt));
  83     pstate = 0;
  84     tl = 0;
  85     pil = 0;
  86     cwp = 0;
  87     //cansave = 0;
  88     //canrestore = 0;
  89     //cleanwin = 0;
  90     //otherwin = 0;
  91     //wstate = 0;
  92     gl = 0;
  93     //In a T1, bit 11 is apparently always 1
  94     hpstate = (1 << 11);
  95     memset(htstate, 0, sizeof(htstate));
  96     hintp = 0;
  97     htba = 0;
  98     hstick_cmpr = 0;
  99     //This is set this way in Legion for some reason
 100     strandStatusReg = 0x50000;
 101     fsr = 0;
 102
 103     priContext = 0;
 104     secContext = 0;
 105     partId = 0;
 106     lsuCtrlReg = 0;
 107
 108     iTlbC0TsbPs0 = 0;
 109     iTlbC0TsbPs1 = 0;
 110     iTlbC0Config = 0;
 111     iTlbCXTsbPs0 = 0;
 112     iTlbCXTsbPs1 = 0;
 113     iTlbCXConfig = 0;
 114     iTlbSfsr = 0;
 115     iTlbTagAccess = 0;
 116
 117     dTlbC0TsbPs0 = 0;
 118     dTlbC0TsbPs1 = 0;
 119     dTlbC0Config = 0;
 120     dTlbCXTsbPs0 = 0;
 121     dTlbCXTsbPs1 = 0;
 122     dTlbCXConfig = 0;
 123     dTlbSfsr = 0;
 124     dTlbSfar = 0;
 125     dTlbTagAccess = 0;
 126
 127     memset(scratchPad, 0, sizeof(scratchPad));
 128 }
 129
 130 MiscReg MiscRegFile::readReg(int miscReg)
 131 {
 132     switch (miscReg) {
 133       case MISCREG_TLB_DATA:
 134         /* Package up all the data for the tlb:
 135          * 6666555555555544444444443333333333222222222211111111110000000000
 136          * 3210987654321098765432109876543210987654321098765432109876543210
 137          *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
 138          *                                                           ||||^red
 139          *                                                           |||^priv
 140          *                                                           ||^am
 141          *                                                           |^lsuim
 142          *                                                           ^lsudm
 143          */
 144         return bits((uint64_t)hpstate,2,2) |
 145                bits((uint64_t)hpstate,5,5) << 1 |
 146                bits((uint64_t)pstate,3,2) << 2 |
 147                bits((uint64_t)lsuCtrlReg,3,2) << 4 |
 148                bits((uint64_t)partId,7,0) << 8 |
 149                bits((uint64_t)tl,2,0) << 16 |
 150                (uint64_t)priContext << 32 |
 151                (uint64_t)secContext << 48;
 152
 153       //case MISCREG_Y:
 154       //  return y;
 155       //case MISCREG_CCR:
 156       //  return ccr;
 157       case MISCREG_ASI:
 158         return asi;
 159       case MISCREG_FPRS:
 160         return fprs;
 161       case MISCREG_TICK:
 162         return tick;
 163       case MISCREG_PCR:
 164         panic("PCR not implemented\n");
 165       case MISCREG_PIC:
 166         panic("PIC not implemented\n");
 167       case MISCREG_GSR:
 168         return gsr;
 169       case MISCREG_SOFTINT:
 170         return softint;
 171       case MISCREG_TICK_CMPR:
 172         return tick_cmpr;
 173       case MISCREG_STICK:
 174         return stick;
 175       case MISCREG_STICK_CMPR:
 176         return stick_cmpr;
 177
 178         /** Privilged Registers */
 179       case MISCREG_TPC:
 180         return tpc[tl-1];
 181       case MISCREG_TNPC:
 182         return tnpc[tl-1];
 183       case MISCREG_TSTATE:
 184         return tstate[tl-1];
 185       case MISCREG_TT:
 186         return tt[tl-1];
 187       case MISCREG_PRIVTICK:
 188         panic("Priviliged access to tick registers not implemented\n");
 189       case MISCREG_TBA:
 190         return tba;
 191       case MISCREG_PSTATE:
 192         return pstate;
 193       case MISCREG_TL:
 194         return tl;
 195       case MISCREG_PIL:
 196         return pil;
 197       case MISCREG_CWP:
 198         return cwp;
 199       //case MISCREG_CANSAVE:
 200       //  return cansave;
 201       //case MISCREG_CANRESTORE:
 202       //  return canrestore;
 203       //case MISCREG_CLEANWIN:
 204       //  return cleanwin;
 205       //case MISCREG_OTHERWIN:
 206       //  return otherwin;
 207       //case MISCREG_WSTATE:
 208       //  return wstate;
 209       case MISCREG_GL:
 210         return gl;
 211
 212         /** Hyper privileged registers */
 213       case MISCREG_HPSTATE:
 214         return hpstate;
 215       case MISCREG_HTSTATE:
 216         return htstate[tl-1];
 217       case MISCREG_HINTP:
 218         panic("HINTP not implemented\n");
 219       case MISCREG_HTBA:
 220         return htba;
 221       case MISCREG_HVER:
 222         return NWindows | MaxTL << 8 | MaxGL << 16;
 223       case MISCREG_STRAND_STS_REG:
 224         return strandStatusReg;
 225       case MISCREG_HSTICK_CMPR:
 226         return hstick_cmpr;
 227
 228         /** Floating Point Status Register */
 229       case MISCREG_FSR:
 230         return fsr;
 231
 232       case MISCREG_MMU_P_CONTEXT:
 233         return priContext;
 234       case MISCREG_MMU_S_CONTEXT:
 235         return secContext;
 236       case MISCREG_MMU_PART_ID:
 237         return partId;
 238       case MISCREG_MMU_LSU_CTRL:
 239         return lsuCtrlReg;
 240
 241       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 242         return iTlbC0TsbPs0;
 243       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 244         return iTlbC0TsbPs1;
 245       case MISCREG_MMU_ITLB_C0_CONFIG:
 246         return iTlbC0Config;
 247       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 248         return iTlbCXTsbPs0;
 249       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 250         return iTlbCXTsbPs1;
 251       case MISCREG_MMU_ITLB_CX_CONFIG:
 252         return iTlbCXConfig;
 253       case MISCREG_MMU_ITLB_SFSR:
 254         return iTlbSfsr;
 255       case MISCREG_MMU_ITLB_TAG_ACCESS:
 256         return iTlbTagAccess;
 257
 258       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 259         return dTlbC0TsbPs0;
 260       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 261         return dTlbC0TsbPs1;
 262       case MISCREG_MMU_DTLB_C0_CONFIG:
 263         return dTlbC0Config;
 264       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 265         return dTlbCXTsbPs0;
 266       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 267         return dTlbCXTsbPs1;
 268       case MISCREG_MMU_DTLB_CX_CONFIG:
 269         return dTlbCXConfig;
 270       case MISCREG_MMU_DTLB_SFSR:
 271         return dTlbSfsr;
 272       case MISCREG_MMU_DTLB_SFAR:
 273         return dTlbSfar;
 274       case MISCREG_MMU_DTLB_TAG_ACCESS:
 275         return dTlbTagAccess;
 276
 277       case MISCREG_SCRATCHPAD_R0:
 278         return scratchPad[0];
 279       case MISCREG_SCRATCHPAD_R1:
 280         return scratchPad[1];
 281       case MISCREG_SCRATCHPAD_R2:
 282         return scratchPad[2];
 283       case MISCREG_SCRATCHPAD_R3:
 284         return scratchPad[3];
 285       case MISCREG_SCRATCHPAD_R4:
 286         return scratchPad[4];
 287       case MISCREG_SCRATCHPAD_R5:
 288         return scratchPad[5];
 289       case MISCREG_SCRATCHPAD_R6:
 290         return scratchPad[6];
 291       case MISCREG_SCRATCHPAD_R7:
 292         return scratchPad[7];
 293       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 294         return cpu_mondo_head;
 295       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 296         return cpu_mondo_tail;
 297       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 298         return dev_mondo_head;
 299       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 300         return dev_mondo_tail;
 301       case MISCREG_QUEUE_RES_ERROR_HEAD:
 302         return res_error_head;
 303       case MISCREG_QUEUE_RES_ERROR_TAIL:
 304         return res_error_tail;
 305       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 306         return nres_error_head;
 307       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 308         return nres_error_tail;
 309       default:
 310         panic("Miscellaneous register %d not implemented\n", miscReg);
 311     }
 312 }
 313
 314 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 315 {
 316     switch (miscReg) {
 317         // tick and stick are aliased to each other in niagra
 318         // well store the tick data in stick and the interrupt bit in tick
 319       case MISCREG_STICK:
 320       case MISCREG_TICK:
 321       case MISCREG_PRIVTICK:
 322         // I'm not sure why legion ignores the lowest two bits, but we'll go
 323         // with it
 324         // change from curCycle() to instCount() until we're done with legion
 325         DPRINTFN("Instruction Count when TICK read: %#X stick=%#X\n",
 326                 tc->getCpuPtr()->instCount(), stick);
 327         return mbits(tc->getCpuPtr()->instCount() + (int32_t)stick,62,2) |
 328                mbits(tick,63,63);
 329       case MISCREG_FPRS:
 330         warn("FPRS register read and FPU stuff not really implemented\n");
 331         return fprs;
 332       case MISCREG_PCR:
 333       case MISCREG_PIC:
 334         panic("Performance Instrumentation not impl\n");
 335         /** Floating Point Status Register */
 336       case MISCREG_FSR:
 337         warn("Reading FSR Floating Point not implemented\n");
 338         break;
 339       case MISCREG_SOFTINT_CLR:
 340       case MISCREG_SOFTINT_SET:
 341         panic("Can read from softint clr/set\n");
 342       case MISCREG_SOFTINT:
 343       case MISCREG_TICK_CMPR:
 344       case MISCREG_STICK_CMPR:
 345       case MISCREG_HINTP:
 346       case MISCREG_HTSTATE:
 347       case MISCREG_HTBA:
 348       case MISCREG_HVER:
 349       case MISCREG_STRAND_STS_REG:
 350       case MISCREG_HSTICK_CMPR:
 351       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 352       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 353       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 354       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 355       case MISCREG_QUEUE_RES_ERROR_HEAD:
 356       case MISCREG_QUEUE_RES_ERROR_TAIL:
 357       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 358       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 359 #if FULL_SYSTEM
 360       case MISCREG_HPSTATE:
 361         return readFSRegWithEffect(miscReg, tc);
 362 #else
 363       case MISCREG_HPSTATE:
 364         //HPSTATE is special because because sometimes in privilege checks for instructions
 365         //it will read HPSTATE to make sure the priv. level is ok
 366         //So, we'll just have to tell it it isn't, instead of panicing.
 367         return 0;
 368
 369       panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
 370 #endif
 371
 372     }
 373     return readReg(miscReg);
 374 }
 375
 376 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 377 {
 378     switch (miscReg) {
 379 //      case MISCREG_Y:
 380 //        y = val;
 381 //        break;
 382 //      case MISCREG_CCR:
 383 //        ccr = val;
 384 //        break;
 385       case MISCREG_ASI:
 386         asi = val;
 387         break;
 388       case MISCREG_FPRS:
 389         warn("FPU not really implemented writing %#X to FPRS\n", val);
 390         fprs = val;
 391         break;
 392       case MISCREG_TICK:
 393         tick = val;
 394         break;
 395       case MISCREG_PCR:
 396         panic("PCR not implemented\n");
 397       case MISCREG_PIC:
 398         panic("PIC not implemented\n");
 399       case MISCREG_GSR:
 400         gsr = val;
 401         break;
 402       case MISCREG_SOFTINT:
 403         softint |= val;
 404         break;
 405       case MISCREG_TICK_CMPR:
 406         tick_cmpr = val;
 407         break;
 408       case MISCREG_STICK:
 409         stick = val;
 410         break;
 411       case MISCREG_STICK_CMPR:
 412         stick_cmpr = val;
 413         break;
 414
 415         /** Privilged Registers */
 416       case MISCREG_TPC:
 417         tpc[tl-1] = val;
 418         break;
 419       case MISCREG_TNPC:
 420         tnpc[tl-1] = val;
 421         break;
 422       case MISCREG_TSTATE:
 423         tstate[tl-1] = val;
 424         break;
 425       case MISCREG_TT:
 426         tt[tl-1] = val;
 427         break;
 428       case MISCREG_PRIVTICK:
 429         panic("Priviliged access to tick regesiters not implemented\n");
 430       case MISCREG_TBA:
 431         // clear lower 7 bits on writes.
 432         tba = val & ULL(~0x7FFF);
 433         break;
 434       case MISCREG_PSTATE:
 435         pstate = (val & PSTATE_MASK);
 436         break;
 437       case MISCREG_TL:
 438         tl = val;
 439         break;
 440       case MISCREG_PIL:
 441         pil = val;
 442         break;
 443       case MISCREG_CWP:
 444         cwp = val;
 445         break;
 446 //      case MISCREG_CANSAVE:
 447 //        cansave = val;
 448 //        break;
 449 //      case MISCREG_CANRESTORE:
 450 //        canrestore = val;
 451 //        break;
 452 //      case MISCREG_CLEANWIN:
 453 //        cleanwin = val;
 454 //        break;
 455 //      case MISCREG_OTHERWIN:
 456 //        otherwin = val;
 457 //        break;
 458 //      case MISCREG_WSTATE:
 459 //        wstate = val;
 460 //        break;
 461       case MISCREG_GL:
 462         gl = val;
 463         break;
 464
 465         /** Hyper privileged registers */
 466       case MISCREG_HPSTATE:
 467         hpstate = val;
 468         break;
 469       case MISCREG_HTSTATE:
 470         htstate[tl-1] = val;
 471         break;
 472       case MISCREG_HINTP:
 473         panic("HINTP not implemented\n");
 474       case MISCREG_HTBA:
 475         htba = val;
 476         break;
 477       case MISCREG_STRAND_STS_REG:
 478         strandStatusReg = val;
 479         break;
 480       case MISCREG_HSTICK_CMPR:
 481         hstick_cmpr = val;
 482         break;
 483
 484         /** Floating Point Status Register */
 485       case MISCREG_FSR:
 486         fsr = val;
 487         break;
 488
 489       case MISCREG_MMU_P_CONTEXT:
 490         priContext = val;
 491         break;
 492       case MISCREG_MMU_S_CONTEXT:
 493         secContext = val;
 494         break;
 495       case MISCREG_MMU_PART_ID:
 496         partId = val;
 497         break;
 498       case MISCREG_MMU_LSU_CTRL:
 499         lsuCtrlReg = val;
 500         break;
 501
 502       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 503         iTlbC0TsbPs0 = val;
 504         break;
 505       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 506         iTlbC0TsbPs1 = val;
 507         break;
 508       case MISCREG_MMU_ITLB_C0_CONFIG:
 509         iTlbC0Config = val;
 510         break;
 511       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 512         iTlbCXTsbPs0 = val;
 513         break;
 514       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 515         iTlbCXTsbPs1 = val;
 516         break;
 517       case MISCREG_MMU_ITLB_CX_CONFIG:
 518         iTlbCXConfig = val;
 519         break;
 520       case MISCREG_MMU_ITLB_SFSR:
 521         iTlbSfsr = val;
 522         break;
 523       case MISCREG_MMU_ITLB_TAG_ACCESS:
 524         iTlbTagAccess = val;
 525         break;
 526
 527       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 528         dTlbC0TsbPs0 = val;
 529         break;
 530       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 531         dTlbC0TsbPs1 = val;
 532         break;
 533       case MISCREG_MMU_DTLB_C0_CONFIG:
 534         dTlbC0Config = val;
 535         break;
 536       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 537         dTlbCXTsbPs0 = val;
 538         break;
 539       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 540         dTlbCXTsbPs1 = val;
 541         break;
 542       case MISCREG_MMU_DTLB_CX_CONFIG:
 543         dTlbCXConfig = val;
 544         break;
 545       case MISCREG_MMU_DTLB_SFSR:
 546         dTlbSfsr = val;
 547         break;
 548       case MISCREG_MMU_DTLB_SFAR:
 549         dTlbSfar = val;
 550         break;
 551       case MISCREG_MMU_DTLB_TAG_ACCESS:
 552         dTlbTagAccess = val;
 553         break;
 554
 555       case MISCREG_SCRATCHPAD_R0:
 556         scratchPad[0] = val;
 557         break;
 558       case MISCREG_SCRATCHPAD_R1:
 559         scratchPad[1] = val;
 560         break;
 561       case MISCREG_SCRATCHPAD_R2:
 562         scratchPad[2] = val;
 563         break;
 564       case MISCREG_SCRATCHPAD_R3:
 565         scratchPad[3] = val;
 566         break;
 567       case MISCREG_SCRATCHPAD_R4:
 568         scratchPad[4] = val;
 569         break;
 570       case MISCREG_SCRATCHPAD_R5:
 571         scratchPad[5] = val;
 572         break;
 573       case MISCREG_SCRATCHPAD_R6:
 574         scratchPad[6] = val;
 575         break;
 576       case MISCREG_SCRATCHPAD_R7:
 577         scratchPad[7] = val;
 578         break;
 579       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 580         cpu_mondo_head = val;
 581         break;
 582       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 583         cpu_mondo_tail = val;
 584         break;
 585       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 586         dev_mondo_head = val;
 587         break;
 588       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 589         dev_mondo_tail = val;
 590         break;
 591       case MISCREG_QUEUE_RES_ERROR_HEAD:
 592         res_error_head = val;
 593         break;
 594       case MISCREG_QUEUE_RES_ERROR_TAIL:
 595         res_error_tail = val;
 596         break;
 597       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 598         nres_error_head = val;
 599         break;
 600       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 601         nres_error_tail = val;
 602         break;
 603
 604       default:
 605         panic("Miscellaneous register %d not implemented\n", miscReg);
 606     }
 607 }
 608
 609 void MiscRegFile::setRegWithEffect(int miscReg,
 610         const MiscReg &val, ThreadContext * tc)
 611 {
 612     switch (miscReg) {
 613       case MISCREG_STICK:
 614       case MISCREG_TICK:
 615         // stick and tick are same thing on niagra
 616         // use stick for offset and tick for holding intrrupt bit
 617         stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
 618         tick = mbits(val,63,63);
 619         DPRINTFN("Writing TICK=%#X\n", val);
 620         break;
 621       case MISCREG_FPRS:
 622         //Configure the fpu based on the fprs
 623         break;
 624       case MISCREG_PCR:
 625         //Set up performance counting based on pcr value
 626         break;
 627       case MISCREG_PSTATE:
 628         pstate = val & PSTATE_MASK;
 629         return;
 630       case MISCREG_TL:
 631         tl = val;
 632         return;
 633       case MISCREG_CWP:
 634         tc->changeRegFileContext(CONTEXT_CWP, val);
 635         break;
 636       case MISCREG_GL:
 637         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 638         break;
 639       case MISCREG_PIL:
 640       case MISCREG_SOFTINT:
 641       case MISCREG_TICK_CMPR:
 642       case MISCREG_STICK_CMPR:
 643       case MISCREG_HINTP:
 644       case MISCREG_HTSTATE:
 645       case MISCREG_HTBA:
 646       case MISCREG_HVER:
 647       case MISCREG_STRAND_STS_REG:
 648       case MISCREG_HSTICK_CMPR:
 649       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 650       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 651       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 652       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 653       case MISCREG_QUEUE_RES_ERROR_HEAD:
 654       case MISCREG_QUEUE_RES_ERROR_TAIL:
 655       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 656       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 657 #if FULL_SYSTEM
 658       case MISCREG_HPSTATE:
 659         setFSRegWithEffect(miscReg, val, tc);
 660         return;
 661 #else
 662       case MISCREG_HPSTATE:
 663         //HPSTATE is special because normal trap processing saves HPSTATE when
 664         //it goes into a trap, and restores it when it returns.
 665         return;
 666       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 667 #endif
 668     }
 669     setReg(miscReg, val);
 670 }
 671
 672 void MiscRegFile::serialize(std::ostream & os)
 673 {
 674     SERIALIZE_SCALAR(pstate);
 675     SERIALIZE_SCALAR(tba);
 676 //    SERIALIZE_SCALAR(y);
 677     SERIALIZE_SCALAR(pil);
 678     SERIALIZE_SCALAR(gl);
 679     SERIALIZE_SCALAR(cwp);
 680     SERIALIZE_ARRAY(tt, MaxTL);
 681 //    SERIALIZE_SCALAR(ccr);
 682     SERIALIZE_SCALAR(asi);
 683     SERIALIZE_SCALAR(tl);
 684     SERIALIZE_ARRAY(tpc, MaxTL);
 685     SERIALIZE_ARRAY(tnpc, MaxTL);
 686     SERIALIZE_ARRAY(tstate, MaxTL);
 687     SERIALIZE_SCALAR(tick);
 688 //    SERIALIZE_SCALAR(cansave);
 689 //    SERIALIZE_SCALAR(canrestore);
 690 //    SERIALIZE_SCALAR(otherwin);
 691 //    SERIALIZE_SCALAR(cleanwin);
 692 //    SERIALIZE_SCALAR(wstate);
 693     SERIALIZE_SCALAR(fsr);
 694     SERIALIZE_SCALAR(fprs);
 695     SERIALIZE_SCALAR(hpstate);
 696     SERIALIZE_ARRAY(htstate, MaxTL);
 697     SERIALIZE_SCALAR(htba);
 698     SERIALIZE_SCALAR(hstick_cmpr);
 699     SERIALIZE_SCALAR(strandStatusReg);
 700     SERIALIZE_SCALAR(priContext);
 701     SERIALIZE_SCALAR(secContext);
 702     SERIALIZE_SCALAR(partId);
 703     SERIALIZE_SCALAR(lsuCtrlReg);
 704     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 705     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 706     SERIALIZE_SCALAR(iTlbC0Config);
 707     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 708     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 709     SERIALIZE_SCALAR(iTlbCXConfig);
 710     SERIALIZE_SCALAR(iTlbSfsr);
 711     SERIALIZE_SCALAR(iTlbTagAccess);
 712     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 713     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 714     SERIALIZE_SCALAR(dTlbC0Config);
 715     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 716     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 717     SERIALIZE_SCALAR(dTlbSfsr);
 718     SERIALIZE_SCALAR(dTlbSfar);
 719     SERIALIZE_SCALAR(dTlbTagAccess);
 720     SERIALIZE_ARRAY(scratchPad,8);
 721     SERIALIZE_SCALAR(cpu_mondo_head);
 722     SERIALIZE_SCALAR(cpu_mondo_tail);
 723     SERIALIZE_SCALAR(dev_mondo_head);
 724     SERIALIZE_SCALAR(dev_mondo_tail);
 725     SERIALIZE_SCALAR(res_error_head);
 726     SERIALIZE_SCALAR(res_error_tail);
 727     SERIALIZE_SCALAR(nres_error_head);
 728     SERIALIZE_SCALAR(nres_error_tail);
 729 }
 730
 731 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 732 {
 733     UNSERIALIZE_SCALAR(pstate);
 734     UNSERIALIZE_SCALAR(tba);
 735 //    UNSERIALIZE_SCALAR(y);
 736     UNSERIALIZE_SCALAR(pil);
 737     UNSERIALIZE_SCALAR(gl);
 738     UNSERIALIZE_SCALAR(cwp);
 739     UNSERIALIZE_ARRAY(tt, MaxTL);
 740 //    UNSERIALIZE_SCALAR(ccr);
 741     UNSERIALIZE_SCALAR(asi);
 742     UNSERIALIZE_SCALAR(tl);
 743     UNSERIALIZE_ARRAY(tpc, MaxTL);
 744     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 745     UNSERIALIZE_ARRAY(tstate, MaxTL);
 746     UNSERIALIZE_SCALAR(tick);
 747 //    UNSERIALIZE_SCALAR(cansave);
 748 //    UNSERIALIZE_SCALAR(canrestore);
 749 //    UNSERIALIZE_SCALAR(otherwin);
 750 //    UNSERIALIZE_SCALAR(cleanwin);
 751 //    UNSERIALIZE_SCALAR(wstate);
 752     UNSERIALIZE_SCALAR(fsr);
 753     UNSERIALIZE_SCALAR(fprs);
 754     UNSERIALIZE_SCALAR(hpstate);
 755     UNSERIALIZE_ARRAY(htstate, MaxTL);
 756     UNSERIALIZE_SCALAR(htba);
 757     UNSERIALIZE_SCALAR(hstick_cmpr);
 758     UNSERIALIZE_SCALAR(strandStatusReg);
 759     UNSERIALIZE_SCALAR(priContext);
 760     UNSERIALIZE_SCALAR(secContext);
 761     UNSERIALIZE_SCALAR(partId);
 762     UNSERIALIZE_SCALAR(lsuCtrlReg);
 763     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 764     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 765     UNSERIALIZE_SCALAR(iTlbC0Config);
 766     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 767     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 768     UNSERIALIZE_SCALAR(iTlbCXConfig);
 769     UNSERIALIZE_SCALAR(iTlbSfsr);
 770     UNSERIALIZE_SCALAR(iTlbTagAccess);
 771     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 772     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 773     UNSERIALIZE_SCALAR(dTlbC0Config);
 774     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 775     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 776     UNSERIALIZE_SCALAR(dTlbSfsr);
 777     UNSERIALIZE_SCALAR(dTlbSfar);
 778     UNSERIALIZE_SCALAR(dTlbTagAccess);
 779     UNSERIALIZE_ARRAY(scratchPad,8);
 780     UNSERIALIZE_SCALAR(cpu_mondo_head);
 781     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 782     UNSERIALIZE_SCALAR(dev_mondo_head);
 783     UNSERIALIZE_SCALAR(dev_mondo_tail);
 784     UNSERIALIZE_SCALAR(res_error_head);
 785     UNSERIALIZE_SCALAR(res_error_tail);
 786     UNSERIALIZE_SCALAR(nres_error_head);
 787     UNSERIALIZE_SCALAR(nres_error_tail);}