src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 #if FULL_SYSTEM
  41 #include "arch/sparc/system.hh"
  42 #endif
  43
  44 using namespace SparcISA;
  45 using namespace std;
  46
  47 class Checkpoint;
  48
  49 //These functions map register indices to names
  50 string SparcISA::getMiscRegName(RegIndex index)
  51 {
  52     static::string miscRegName[NumMiscRegs] =
  53         {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
  54          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  55          "stick", "stick_cmpr",
  56          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  57          "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  58          "wstate", "gl",
  59          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  60          "hstick_cmpr",
  61          "fsr"};
  62     return miscRegName[index];
  63 }
  64
  65 enum RegMask
  66 {
  67         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  68 };
  69
  70 void MiscRegFile::clear()
  71 {
  72     y = 0;
  73     ccr = 0;
  74     asi = 0;
  75     tick = ULL(1) << 63;
  76     fprs = 0;
  77     gsr = 0;
  78     softint = 0;
  79     tick_cmpr = 0;
  80     stick = 0;
  81     stick_cmpr = 0;
  82     memset(tpc, 0, sizeof(tpc));
  83     memset(tnpc, 0, sizeof(tnpc));
  84     memset(tstate, 0, sizeof(tstate));
  85     memset(tt, 0, sizeof(tt));
  86     pstate = 0;
  87     tl = 0;
  88     pil = 0;
  89     cwp = 0;
  90     cansave = 0;
  91     canrestore = 0;
  92     cleanwin = 0;
  93     otherwin = 0;
  94     wstate = 0;
  95     gl = 0;
  96     //In a T1, bit 11 is apparently always 1
  97     hpstate = (1 << 11);
  98     memset(htstate, 0, sizeof(htstate));
  99     hintp = 0;
 100     htba = 0;
 101     hstick_cmpr = 0;
 102     //This is set this way in Legion for some reason
 103     strandStatusReg = 0x50000;
 104     fsr = 0;
 105
 106     priContext = 0;
 107     secContext = 0;
 108     partId = 0;
 109     lsuCtrlReg = 0;
 110
 111     iTlbC0TsbPs0 = 0;
 112     iTlbC0TsbPs1 = 0;
 113     iTlbC0Config = 0;
 114     iTlbCXTsbPs0 = 0;
 115     iTlbCXTsbPs1 = 0;
 116     iTlbCXConfig = 0;
 117     iTlbSfsr = 0;
 118     iTlbTagAccess = 0;
 119
 120     dTlbC0TsbPs0 = 0;
 121     dTlbC0TsbPs1 = 0;
 122     dTlbC0Config = 0;
 123     dTlbCXTsbPs0 = 0;
 124     dTlbCXTsbPs1 = 0;
 125     dTlbCXConfig = 0;
 126     dTlbSfsr = 0;
 127     dTlbSfar = 0;
 128     dTlbTagAccess = 0;
 129
 130     memset(scratchPad, 0, sizeof(scratchPad));
 131 }
 132
 133 MiscReg MiscRegFile::readReg(int miscReg)
 134 {
 135     switch (miscReg) {
 136         case MISCREG_Y:
 137           return y;
 138         case MISCREG_CCR:
 139           return ccr;
 140         case MISCREG_ASI:
 141           return asi;
 142         case MISCREG_FPRS:
 143           return fprs;
 144         case MISCREG_TICK:
 145            return tick;
 146         case MISCREG_PCR:
 147           panic("PCR not implemented\n");
 148         case MISCREG_PIC:
 149           panic("PIC not implemented\n");
 150         case MISCREG_GSR:
 151           return gsr;
 152         case MISCREG_SOFTINT:
 153            return softint;
 154         case MISCREG_TICK_CMPR:
 155            return tick_cmpr;
 156         case MISCREG_STICK:
 157            return stick;
 158         case MISCREG_STICK_CMPR:
 159            return stick_cmpr;
 160
 161         /** Privilged Registers */
 162         case MISCREG_TPC:
 163           return tpc[tl-1];
 164         case MISCREG_TNPC:
 165           return tnpc[tl-1];
 166         case MISCREG_TSTATE:
 167           return tstate[tl-1];
 168         case MISCREG_TT:
 169           return tt[tl-1];
 170         case MISCREG_PRIVTICK:
 171           panic("Priviliged access to tick registers not implemented\n");
 172         case MISCREG_TBA:
 173           return tba;
 174         case MISCREG_PSTATE:
 175           return pstate;
 176         case MISCREG_TL:
 177           return tl;
 178         case MISCREG_PIL:
 179           return pil;
 180         case MISCREG_CWP:
 181           return cwp;
 182         case MISCREG_CANSAVE:
 183           return cansave;
 184         case MISCREG_CANRESTORE:
 185           return canrestore;
 186         case MISCREG_CLEANWIN:
 187           return cleanwin;
 188         case MISCREG_OTHERWIN:
 189           return otherwin;
 190         case MISCREG_WSTATE:
 191           return wstate;
 192         case MISCREG_GL:
 193           return gl;
 194
 195         /** Hyper privileged registers */
 196         case MISCREG_HPSTATE:
 197           return hpstate;
 198         case MISCREG_HTSTATE:
 199           return htstate[tl-1];
 200         case MISCREG_HINTP:
 201           panic("HINTP not implemented\n");
 202         case MISCREG_HTBA:
 203           return htba;
 204         case MISCREG_HVER:
 205           return NWindows | MaxTL << 8 | MaxGL << 16;
 206         case MISCREG_STRAND_STS_REG:
 207           return strandStatusReg;
 208         case MISCREG_HSTICK_CMPR:
 209           return hstick_cmpr;
 210
 211         /** Floating Point Status Register */
 212         case MISCREG_FSR:
 213           return fsr;
 214
 215         case MISCREG_MMU_P_CONTEXT:
 216           return priContext;
 217         case MISCREG_MMU_S_CONTEXT:
 218           return secContext;
 219         case MISCREG_MMU_PART_ID:
 220           return partId;
 221         case MISCREG_MMU_LSU_CTRL:
 222           return lsuCtrlReg;
 223
 224         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 225           return iTlbC0TsbPs0;
 226         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 227           return iTlbC0TsbPs1;
 228         case MISCREG_MMU_ITLB_C0_CONFIG:
 229           return iTlbC0Config;
 230         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 231           return iTlbCXTsbPs0;
 232         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 233           return iTlbCXTsbPs1;
 234         case MISCREG_MMU_ITLB_CX_CONFIG:
 235           return iTlbCXConfig;
 236         case MISCREG_MMU_ITLB_SFSR:
 237           return iTlbSfsr;
 238         case MISCREG_MMU_ITLB_TAG_ACCESS:
 239           return iTlbTagAccess;
 240
 241         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 242           return dTlbC0TsbPs0;
 243         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 244           return dTlbC0TsbPs1;
 245         case MISCREG_MMU_DTLB_C0_CONFIG:
 246           return dTlbC0Config;
 247         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 248           return dTlbCXTsbPs0;
 249         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 250           return dTlbCXTsbPs1;
 251         case MISCREG_MMU_DTLB_CX_CONFIG:
 252           return dTlbCXConfig;
 253         case MISCREG_MMU_DTLB_SFSR:
 254           return dTlbSfsr;
 255         case MISCREG_MMU_DTLB_SFAR:
 256           return dTlbSfar;
 257         case MISCREG_MMU_DTLB_TAG_ACCESS:
 258           return dTlbTagAccess;
 259
 260         case MISCREG_SCRATCHPAD_R0:
 261           return scratchPad[0];
 262         case MISCREG_SCRATCHPAD_R1:
 263           return scratchPad[1];
 264         case MISCREG_SCRATCHPAD_R2:
 265           return scratchPad[2];
 266         case MISCREG_SCRATCHPAD_R3:
 267           return scratchPad[3];
 268         case MISCREG_SCRATCHPAD_R4:
 269           return scratchPad[4];
 270         case MISCREG_SCRATCHPAD_R5:
 271           return scratchPad[5];
 272         case MISCREG_SCRATCHPAD_R6:
 273           return scratchPad[6];
 274         case MISCREG_SCRATCHPAD_R7:
 275           return scratchPad[7];
 276
 277         default:
 278           panic("Miscellaneous register %d not implemented\n", miscReg);
 279     }
 280 }
 281
 282 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 283 {
 284     switch (miscReg) {
 285         // tick and stick are aliased to each other in niagra
 286         case MISCREG_STICK:
 287         case MISCREG_TICK:
 288         case MISCREG_PRIVTICK:
 289           // I'm not sure why legion ignores the lowest two bits, but we'll go
 290           // with it
 291           // change from curCycle() to instCount() until we're done with legion
 292           DPRINTFN("Instruction Count when STICK read: %#X\n",
 293                   tc->getCpuPtr()->instCount());
 294           uint64_t t1 =  mbits(tc->getCpuPtr()->instCount() - (tick &
 295                       mask(63)),62,2);
 296           uint64_t t2 = mbits(tick,63,63) ;
 297           return t1 | t2;
 298         case MISCREG_FPRS:
 299           panic("FPU not implemented\n");
 300         case MISCREG_PCR:
 301         case MISCREG_PIC:
 302           panic("Performance Instrumentation not impl\n");
 303         /** Floating Point Status Register */
 304         case MISCREG_FSR:
 305           panic("Floating Point not implemented\n");
 306 //We'll include this only in FS so we don't need the SparcSystem type around
 307 //in SE.
 308 /*#if FULL_SYSTEM
 309         case MISCREG_STICK:
 310           SparcSystem *sys;
 311           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 312           assert(sys != NULL);
 313           return curTick/Clock::Int::ns - sys->sysTick | (stick & ~(mask(63)));
 314 #endif*/
 315         case MISCREG_HVER:
 316           return NWindows | MaxTL << 8 | MaxGL << 16;
 317     }
 318     return readReg(miscReg);
 319 }
 320
 321 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 322 {
 323     switch (miscReg) {
 324         case MISCREG_Y:
 325           y = val;
 326           break;
 327         case MISCREG_CCR:
 328           ccr = val;
 329           break;
 330         case MISCREG_ASI:
 331           asi = val;
 332           break;
 333         case MISCREG_FPRS:
 334           fprs = val;
 335           break;
 336         case MISCREG_TICK:
 337           tick = val;
 338           break;
 339         case MISCREG_PCR:
 340           panic("PCR not implemented\n");
 341         case MISCREG_PIC:
 342           panic("PIC not implemented\n");
 343         case MISCREG_GSR:
 344           gsr = val;
 345           break;
 346         case MISCREG_SOFTINT:
 347           softint = val;
 348           break;
 349         case MISCREG_TICK_CMPR:
 350           tick_cmpr = val;
 351           break;
 352         case MISCREG_STICK:
 353           stick = val;
 354           break;
 355         case MISCREG_STICK_CMPR:
 356           stick_cmpr = val;
 357           break;
 358
 359         /** Privilged Registers */
 360         case MISCREG_TPC:
 361           tpc[tl-1] = val;
 362           break;
 363         case MISCREG_TNPC:
 364           tnpc[tl-1] = val;
 365           break;
 366         case MISCREG_TSTATE:
 367           tstate[tl-1] = val;
 368           break;
 369         case MISCREG_TT:
 370           tt[tl-1] = val;
 371           break;
 372         case MISCREG_PRIVTICK:
 373           panic("Priviliged access to tick regesiters not implemented\n");
 374         case MISCREG_TBA:
 375           // clear lower 7 bits on writes.
 376           tba = val & ULL(~0x7FFF);
 377           break;
 378         case MISCREG_PSTATE:
 379           pstate = (val & PSTATE_MASK);
 380           break;
 381         case MISCREG_TL:
 382           tl = val;
 383           break;
 384         case MISCREG_PIL:
 385           pil = val;
 386           break;
 387         case MISCREG_CWP:
 388           cwp = val;
 389           break;
 390         case MISCREG_CANSAVE:
 391           cansave = val;
 392           break;
 393         case MISCREG_CANRESTORE:
 394           canrestore = val;
 395           break;
 396         case MISCREG_CLEANWIN:
 397           cleanwin = val;
 398           break;
 399         case MISCREG_OTHERWIN:
 400           otherwin = val;
 401           break;
 402         case MISCREG_WSTATE:
 403           wstate = val;
 404           break;
 405         case MISCREG_GL:
 406           gl = val;
 407           break;
 408
 409         /** Hyper privileged registers */
 410         case MISCREG_HPSTATE:
 411           hpstate = val;
 412           break;
 413         case MISCREG_HTSTATE:
 414           htstate[tl-1] = val;
 415           break;
 416         case MISCREG_HINTP:
 417           panic("HINTP not implemented\n");
 418         case MISCREG_HTBA:
 419           htba = val;
 420           break;
 421         case MISCREG_STRAND_STS_REG:
 422           strandStatusReg = val;
 423           break;
 424         case MISCREG_HSTICK_CMPR:
 425           hstick_cmpr = val;
 426           break;
 427
 428         /** Floating Point Status Register */
 429         case MISCREG_FSR:
 430           fsr = val;
 431           break;
 432
 433         case MISCREG_MMU_P_CONTEXT:
 434           priContext = val;
 435           break;
 436         case MISCREG_MMU_S_CONTEXT:
 437           secContext = val;
 438           break;
 439         case MISCREG_MMU_PART_ID:
 440           partId = val;
 441           break;
 442         case MISCREG_MMU_LSU_CTRL:
 443           lsuCtrlReg = val;
 444           break;
 445
 446         case MISCREG_MMU_ITLB_C0_TSB_PS0:
 447           iTlbC0TsbPs0 = val;
 448           break;
 449         case MISCREG_MMU_ITLB_C0_TSB_PS1:
 450           iTlbC0TsbPs1 = val;
 451           break;
 452         case MISCREG_MMU_ITLB_C0_CONFIG:
 453           iTlbC0Config = val;
 454           break;
 455         case MISCREG_MMU_ITLB_CX_TSB_PS0:
 456           iTlbCXTsbPs0 = val;
 457           break;
 458         case MISCREG_MMU_ITLB_CX_TSB_PS1:
 459           iTlbCXTsbPs1 = val;
 460           break;
 461         case MISCREG_MMU_ITLB_CX_CONFIG:
 462           iTlbCXConfig = val;
 463           break;
 464         case MISCREG_MMU_ITLB_SFSR:
 465           iTlbSfsr = val;
 466           break;
 467         case MISCREG_MMU_ITLB_TAG_ACCESS:
 468           iTlbTagAccess = val;
 469           break;
 470
 471         case MISCREG_MMU_DTLB_C0_TSB_PS0:
 472           dTlbC0TsbPs0 = val;
 473           break;
 474         case MISCREG_MMU_DTLB_C0_TSB_PS1:
 475           dTlbC0TsbPs1 = val;
 476           break;
 477         case MISCREG_MMU_DTLB_C0_CONFIG:
 478           dTlbC0Config = val;
 479           break;
 480         case MISCREG_MMU_DTLB_CX_TSB_PS0:
 481           dTlbCXTsbPs0 = val;
 482           break;
 483         case MISCREG_MMU_DTLB_CX_TSB_PS1:
 484           dTlbCXTsbPs1 = val;
 485           break;
 486         case MISCREG_MMU_DTLB_CX_CONFIG:
 487           dTlbCXConfig = val;
 488           break;
 489         case MISCREG_MMU_DTLB_SFSR:
 490           dTlbSfsr = val;
 491           break;
 492         case MISCREG_MMU_DTLB_SFAR:
 493           dTlbSfar = val;
 494           break;
 495         case MISCREG_MMU_DTLB_TAG_ACCESS:
 496           dTlbTagAccess = val;
 497           break;
 498
 499         case MISCREG_SCRATCHPAD_R0:
 500            scratchPad[0] = val;
 501         case MISCREG_SCRATCHPAD_R1:
 502            scratchPad[1] = val;
 503         case MISCREG_SCRATCHPAD_R2:
 504            scratchPad[2] = val;
 505         case MISCREG_SCRATCHPAD_R3:
 506            scratchPad[3] = val;
 507         case MISCREG_SCRATCHPAD_R4:
 508            scratchPad[4] = val;
 509         case MISCREG_SCRATCHPAD_R5:
 510            scratchPad[5] = val;
 511         case MISCREG_SCRATCHPAD_R6:
 512            scratchPad[6] = val;
 513         case MISCREG_SCRATCHPAD_R7:
 514            scratchPad[7] = val;
 515
 516         default:
 517           panic("Miscellaneous register %d not implemented\n", miscReg);
 518     }
 519 }
 520
 521 void MiscRegFile::setRegWithEffect(int miscReg,
 522         const MiscReg &val, ThreadContext * tc)
 523 {
 524     const uint64_t Bit64 = (1ULL << 63);
 525 #if FULL_SYSTEM
 526     uint64_t time;
 527     SparcSystem *sys;
 528 #endif
 529     switch (miscReg) {
 530         case MISCREG_STICK:
 531         case MISCREG_TICK:
 532           // change from curCycle() to instCount() until we're done with legion
 533           tick = tc->getCpuPtr()->instCount() - val  & ~Bit64;
 534           tick |= val & Bit64;
 535           break;
 536         case MISCREG_FPRS:
 537           //Configure the fpu based on the fprs
 538           break;
 539         case MISCREG_PCR:
 540           //Set up performance counting based on pcr value
 541           break;
 542         case MISCREG_PSTATE:
 543           pstate = val & PSTATE_MASK;
 544           return;
 545         case MISCREG_TL:
 546           tl = val;
 547           return;
 548         case MISCREG_CWP:
 549           tc->changeRegFileContext(CONTEXT_CWP, val);
 550           break;
 551         case MISCREG_GL:
 552           tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 553           break;
 554         case MISCREG_SOFTINT:
 555           //We need to inject interrupts, and or notify the interrupt
 556           //object that it needs to use a different interrupt level.
 557           //Any newly appropriate interrupts will happen when the cpu gets
 558           //around to checking for them. This might not be quite what we
 559           //want.
 560           break;
 561         case MISCREG_SOFTINT_CLR:
 562           //Do whatever this is supposed to do...
 563           break;
 564         case MISCREG_SOFTINT_SET:
 565           //Do whatever this is supposed to do...
 566           break;
 567 #if FULL_SYSTEM
 568         case MISCREG_TICK_CMPR:
 569           if (tickCompare == NULL)
 570               tickCompare = new TickCompareEvent(this, tc);
 571           setReg(miscReg, val);
 572           if ((tick_cmpr & mask(63)) && tickCompare->scheduled())
 573                   tickCompare->deschedule();
 574           time = (tick_cmpr & mask(63)) - (tick & mask(63));
 575           if (!(tick_cmpr & ~mask(63)) && time > 0)
 576               tickCompare->schedule(time * tc->getCpuPtr()->cycles(1));
 577           break;
 578 #endif
 579         case MISCREG_PIL:
 580           //We need to inject interrupts, and or notify the interrupt
 581           //object that it needs to use a different interrupt level.
 582           //Any newly appropriate interrupts will happen when the cpu gets
 583           //around to checking for them. This might not be quite what we
 584           //want.
 585           break;
 586 //We'll include this only in FS so we don't need the SparcSystem type around
 587 //in SE.
 588 #if FULL_SYSTEM
 589         // @todo figure out how we're actualy going to do this. In niagra the
 590         // registers are aliased to the same thing (see tick above)
 591         /*case MISCREG_STICK:
 592           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 593           assert(sys != NULL);
 594           sys->sysTick = curTick/Clock::Int::ns - val & ~Bit64;
 595           stick |= val & Bit64;
 596           break;*/
 597         case MISCREG_STICK_CMPR:
 598           if (sTickCompare == NULL)
 599               sTickCompare = new STickCompareEvent(this, tc);
 600           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 601           assert(sys != NULL);
 602           if ((stick_cmpr & ~mask(63)) && sTickCompare->scheduled())
 603                   sTickCompare->deschedule();
 604           time = (stick_cmpr & mask(63)) - sys->sysTick;
 605           if (!(stick_cmpr & ~mask(63)) && time > 0)
 606               sTickCompare->schedule(time * Clock::Int::ns);
 607           break;
 608         case MISCREG_HSTICK_CMPR:
 609           if (hSTickCompare == NULL)
 610               hSTickCompare = new HSTickCompareEvent(this, tc);
 611           sys = dynamic_cast<SparcSystem*>(tc->getSystemPtr());
 612           assert(sys != NULL);
 613           if ((hstick_cmpr & ~mask(63)) && hSTickCompare->scheduled())
 614                   hSTickCompare->deschedule();
 615           int64_t time = (hstick_cmpr & mask(63)) - sys->sysTick;
 616           if (!(hstick_cmpr & ~mask(63)) && time > 0)
 617               hSTickCompare->schedule(time * Clock::Int::ns);
 618           break;
 619 #endif
 620     }
 621     setReg(miscReg, val);
 622 }
 623
 624 void MiscRegFile::serialize(std::ostream & os)
 625 {
 626     SERIALIZE_SCALAR(pstate);
 627     SERIALIZE_SCALAR(tba);
 628     SERIALIZE_SCALAR(y);
 629     SERIALIZE_SCALAR(pil);
 630     SERIALIZE_SCALAR(gl);
 631     SERIALIZE_SCALAR(cwp);
 632     SERIALIZE_ARRAY(tt, MaxTL);
 633     SERIALIZE_SCALAR(ccr);
 634     SERIALIZE_SCALAR(asi);
 635     SERIALIZE_SCALAR(tl);
 636     SERIALIZE_ARRAY(tpc, MaxTL);
 637     SERIALIZE_ARRAY(tnpc, MaxTL);
 638     SERIALIZE_ARRAY(tstate, MaxTL);
 639     SERIALIZE_SCALAR(tick);
 640     SERIALIZE_SCALAR(cansave);
 641     SERIALIZE_SCALAR(canrestore);
 642     SERIALIZE_SCALAR(otherwin);
 643     SERIALIZE_SCALAR(cleanwin);
 644     SERIALIZE_SCALAR(wstate);
 645     SERIALIZE_SCALAR(fsr);
 646     SERIALIZE_SCALAR(fprs);
 647     SERIALIZE_SCALAR(hpstate);
 648     SERIALIZE_ARRAY(htstate, MaxTL);
 649     SERIALIZE_SCALAR(htba);
 650     SERIALIZE_SCALAR(hstick_cmpr);
 651     SERIALIZE_SCALAR(strandStatusReg);
 652     SERIALIZE_SCALAR(priContext);
 653     SERIALIZE_SCALAR(secContext);
 654     SERIALIZE_SCALAR(partId);
 655     SERIALIZE_SCALAR(lsuCtrlReg);
 656     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 657     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 658     SERIALIZE_SCALAR(iTlbC0Config);
 659     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 660     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 661     SERIALIZE_SCALAR(iTlbCXConfig);
 662     SERIALIZE_SCALAR(iTlbSfsr);
 663     SERIALIZE_SCALAR(iTlbTagAccess);
 664     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 665     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 666     SERIALIZE_SCALAR(dTlbC0Config);
 667     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 668     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 669     SERIALIZE_SCALAR(dTlbSfsr);
 670     SERIALIZE_SCALAR(dTlbSfar);
 671     SERIALIZE_SCALAR(dTlbTagAccess);
 672     SERIALIZE_ARRAY(scratchPad,8);
 673 }
 674
 675 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 676 {
 677     UNSERIALIZE_SCALAR(pstate);
 678     UNSERIALIZE_SCALAR(tba);
 679     UNSERIALIZE_SCALAR(y);
 680     UNSERIALIZE_SCALAR(pil);
 681     UNSERIALIZE_SCALAR(gl);
 682     UNSERIALIZE_SCALAR(cwp);
 683     UNSERIALIZE_ARRAY(tt, MaxTL);
 684     UNSERIALIZE_SCALAR(ccr);
 685     UNSERIALIZE_SCALAR(asi);
 686     UNSERIALIZE_SCALAR(tl);
 687     UNSERIALIZE_ARRAY(tpc, MaxTL);
 688     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 689     UNSERIALIZE_ARRAY(tstate, MaxTL);
 690     UNSERIALIZE_SCALAR(tick);
 691     UNSERIALIZE_SCALAR(cansave);
 692     UNSERIALIZE_SCALAR(canrestore);
 693     UNSERIALIZE_SCALAR(otherwin);
 694     UNSERIALIZE_SCALAR(cleanwin);
 695     UNSERIALIZE_SCALAR(wstate);
 696     UNSERIALIZE_SCALAR(fsr);
 697     UNSERIALIZE_SCALAR(fprs);
 698     UNSERIALIZE_SCALAR(hpstate);
 699     UNSERIALIZE_ARRAY(htstate, MaxTL);
 700     UNSERIALIZE_SCALAR(htba);
 701     UNSERIALIZE_SCALAR(hstick_cmpr);
 702     UNSERIALIZE_SCALAR(strandStatusReg);
 703     UNSERIALIZE_SCALAR(priContext);
 704     UNSERIALIZE_SCALAR(secContext);
 705     UNSERIALIZE_SCALAR(partId);
 706     UNSERIALIZE_SCALAR(lsuCtrlReg);
 707     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 708     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 709     UNSERIALIZE_SCALAR(iTlbC0Config);
 710     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 711     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 712     UNSERIALIZE_SCALAR(iTlbCXConfig);
 713     UNSERIALIZE_SCALAR(iTlbSfsr);
 714     UNSERIALIZE_SCALAR(iTlbTagAccess);
 715     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 716     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 717     UNSERIALIZE_SCALAR(dTlbC0Config);
 718     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 719     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 720     UNSERIALIZE_SCALAR(dTlbSfsr);
 721     UNSERIALIZE_SCALAR(dTlbSfar);
 722     UNSERIALIZE_SCALAR(dTlbTagAccess);
 723     UNSERIALIZE_ARRAY(scratchPad,8);}
 724
 725 #if FULL_SYSTEM
 726 void
 727 MiscRegFile::processTickCompare(ThreadContext *tc)
 728 {
 729     panic("tick compare not implemented\n");
 730 }
 731
 732 void
 733 MiscRegFile::processSTickCompare(ThreadContext *tc)
 734 {
 735     panic("tick compare not implemented\n");
 736 }
 737
 738 void
 739 MiscRegFile::processHSTickCompare(ThreadContext *tc)
 740 {
 741     panic("tick compare not implemented\n");
 742 }
 743 #endif