src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  50          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51          "stick", "stick_cmpr",
  52          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
  54          "wstate",*/ "gl",
  55          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56          "hstick_cmpr",
  57          "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", "itbTsbC0Ps0",
  58          "itbTsbC0Ps1", "iTlbC0Cnfg", "itbTsbCXPs0", "itbTsbCXPs1",
  59          "iTlbCXCnfg","iTlbSfsr", "iTlbTagAcs", "dtbTsbC0Ps0",
  60          "dtbTsbC0Ps1", "dTlbC0Cnfg", "dtbTsbCXPs0", "dtbTsbCXPs1",
  61          "dTlbCXCnfg","dTlbSfsr", "dTlbSfar", "dTlbTagAcs",
  62          "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
  63          "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
  64          "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
  65          "nresErrorHead", "nresErrorTail", "TlbData" };
  66
  67     return miscRegName[index];
  68 }
  69
  70 enum RegMask
  71 {
  72         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  73 };
  74
  75 void MiscRegFile::clear()
  76 {
  77     //y = 0;
  78     //ccr = 0;
  79     asi = 0;
  80     tick = ULL(1) << 63;
  81     fprs = 0;
  82     gsr = 0;
  83     softint = 0;
  84     tick_cmpr = 0;
  85     stick = 0;
  86     stick_cmpr = 0;
  87     memset(tpc, 0, sizeof(tpc));
  88     memset(tnpc, 0, sizeof(tnpc));
  89     memset(tstate, 0, sizeof(tstate));
  90     memset(tt, 0, sizeof(tt));
  91     pstate = 0;
  92     tl = 0;
  93     pil = 0;
  94     cwp = 0;
  95     //cansave = 0;
  96     //canrestore = 0;
  97     //cleanwin = 0;
  98     //otherwin = 0;
  99     //wstate = 0;
 100     gl = 0;
 101     //In a T1, bit 11 is apparently always 1
 102     hpstate = (1 << 11);
 103     memset(htstate, 0, sizeof(htstate));
 104     hintp = 0;
 105     htba = 0;
 106     hstick_cmpr = 0;
 107     //This is set this way in Legion for some reason
 108     strandStatusReg = 0x50000;
 109     fsr = 0;
 110
 111     priContext = 0;
 112     secContext = 0;
 113     partId = 0;
 114     lsuCtrlReg = 0;
 115
 116     iTlbC0TsbPs0 = 0;
 117     iTlbC0TsbPs1 = 0;
 118     iTlbC0Config = 0;
 119     iTlbCXTsbPs0 = 0;
 120     iTlbCXTsbPs1 = 0;
 121     iTlbCXConfig = 0;
 122     iTlbSfsr = 0;
 123     iTlbTagAccess = 0;
 124
 125     dTlbC0TsbPs0 = 0;
 126     dTlbC0TsbPs1 = 0;
 127     dTlbC0Config = 0;
 128     dTlbCXTsbPs0 = 0;
 129     dTlbCXTsbPs1 = 0;
 130     dTlbCXConfig = 0;
 131     dTlbSfsr = 0;
 132     dTlbSfar = 0;
 133     dTlbTagAccess = 0;
 134
 135     memset(scratchPad, 0, sizeof(scratchPad));
 136 #if FULL_SYSTEM
 137     tickCompare = NULL;
 138     sTickCompare = NULL;
 139     hSTickCompare = NULL;
 140 #endif
 141 }
 142
 143 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 144 {
 145     switch (miscReg) {
 146       case MISCREG_TLB_DATA:
 147         /* Package up all the data for the tlb:
 148          * 6666555555555544444444443333333333222222222211111111110000000000
 149          * 3210987654321098765432109876543210987654321098765432109876543210
 150          *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
 151          *                                                           ||||^red
 152          *                                                           |||^priv
 153          *                                                           ||^am
 154          *                                                           |^lsuim
 155          *                                                           ^lsudm
 156          */
 157         return bits((uint64_t)hpstate,2,2) |
 158                bits((uint64_t)hpstate,5,5) << 1 |
 159                bits((uint64_t)pstate,3,2) << 2 |
 160                bits((uint64_t)lsuCtrlReg,3,2) << 4 |
 161                bits((uint64_t)partId,7,0) << 8 |
 162                bits((uint64_t)tl,2,0) << 16 |
 163                (uint64_t)priContext << 32 |
 164                (uint64_t)secContext << 48;
 165
 166       //case MISCREG_Y:
 167       //  return y;
 168       //case MISCREG_CCR:
 169       //  return ccr;
 170       case MISCREG_ASI:
 171         return asi;
 172       case MISCREG_FPRS:
 173         return fprs;
 174       case MISCREG_TICK:
 175         return tick;
 176       case MISCREG_PCR:
 177         panic("PCR not implemented\n");
 178       case MISCREG_PIC:
 179         panic("PIC not implemented\n");
 180       case MISCREG_GSR:
 181         return gsr;
 182       case MISCREG_SOFTINT:
 183         return softint;
 184       case MISCREG_TICK_CMPR:
 185         return tick_cmpr;
 186       case MISCREG_STICK:
 187         return stick;
 188       case MISCREG_STICK_CMPR:
 189         return stick_cmpr;
 190
 191         /** Privilged Registers */
 192       case MISCREG_TPC:
 193         return tpc[tl-1];
 194       case MISCREG_TNPC:
 195         return tnpc[tl-1];
 196       case MISCREG_TSTATE:
 197         return tstate[tl-1];
 198       case MISCREG_TT:
 199         return tt[tl-1];
 200       case MISCREG_PRIVTICK:
 201         panic("Priviliged access to tick registers not implemented\n");
 202       case MISCREG_TBA:
 203         return tba;
 204       case MISCREG_PSTATE:
 205         return pstate;
 206       case MISCREG_TL:
 207         return tl;
 208       case MISCREG_PIL:
 209         return pil;
 210       case MISCREG_CWP:
 211         return cwp;
 212       //case MISCREG_CANSAVE:
 213       //  return cansave;
 214       //case MISCREG_CANRESTORE:
 215       //  return canrestore;
 216       //case MISCREG_CLEANWIN:
 217       //  return cleanwin;
 218       //case MISCREG_OTHERWIN:
 219       //  return otherwin;
 220       //case MISCREG_WSTATE:
 221       //  return wstate;
 222       case MISCREG_GL:
 223         return gl;
 224
 225         /** Hyper privileged registers */
 226       case MISCREG_HPSTATE:
 227         return hpstate;
 228       case MISCREG_HTSTATE:
 229         return htstate[tl-1];
 230       case MISCREG_HINTP:
 231         return hintp;
 232       case MISCREG_HTBA:
 233         return htba;
 234       case MISCREG_STRAND_STS_REG:
 235         return strandStatusReg;
 236       case MISCREG_HSTICK_CMPR:
 237         return hstick_cmpr;
 238
 239         /** Floating Point Status Register */
 240       case MISCREG_FSR:
 241         DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
 242         return fsr;
 243
 244       case MISCREG_MMU_P_CONTEXT:
 245         return priContext;
 246       case MISCREG_MMU_S_CONTEXT:
 247         return secContext;
 248       case MISCREG_MMU_PART_ID:
 249         return partId;
 250       case MISCREG_MMU_LSU_CTRL:
 251         return lsuCtrlReg;
 252
 253       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 254         return iTlbC0TsbPs0;
 255       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 256         return iTlbC0TsbPs1;
 257       case MISCREG_MMU_ITLB_C0_CONFIG:
 258         return iTlbC0Config;
 259       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 260         return iTlbCXTsbPs0;
 261       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 262         return iTlbCXTsbPs1;
 263       case MISCREG_MMU_ITLB_CX_CONFIG:
 264         return iTlbCXConfig;
 265       case MISCREG_MMU_ITLB_SFSR:
 266         return iTlbSfsr;
 267       case MISCREG_MMU_ITLB_TAG_ACCESS:
 268         return iTlbTagAccess;
 269
 270       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 271         return dTlbC0TsbPs0;
 272       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 273         return dTlbC0TsbPs1;
 274       case MISCREG_MMU_DTLB_C0_CONFIG:
 275         return dTlbC0Config;
 276       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 277         return dTlbCXTsbPs0;
 278       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 279         return dTlbCXTsbPs1;
 280       case MISCREG_MMU_DTLB_CX_CONFIG:
 281         return dTlbCXConfig;
 282       case MISCREG_MMU_DTLB_SFSR:
 283         return dTlbSfsr;
 284       case MISCREG_MMU_DTLB_SFAR:
 285         return dTlbSfar;
 286       case MISCREG_MMU_DTLB_TAG_ACCESS:
 287         return dTlbTagAccess;
 288
 289       case MISCREG_SCRATCHPAD_R0:
 290         return scratchPad[0];
 291       case MISCREG_SCRATCHPAD_R1:
 292         return scratchPad[1];
 293       case MISCREG_SCRATCHPAD_R2:
 294         return scratchPad[2];
 295       case MISCREG_SCRATCHPAD_R3:
 296         return scratchPad[3];
 297       case MISCREG_SCRATCHPAD_R4:
 298         return scratchPad[4];
 299       case MISCREG_SCRATCHPAD_R5:
 300         return scratchPad[5];
 301       case MISCREG_SCRATCHPAD_R6:
 302         return scratchPad[6];
 303       case MISCREG_SCRATCHPAD_R7:
 304         return scratchPad[7];
 305       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 306         return cpu_mondo_head;
 307       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 308         return cpu_mondo_tail;
 309       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 310         return dev_mondo_head;
 311       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 312         return dev_mondo_tail;
 313       case MISCREG_QUEUE_RES_ERROR_HEAD:
 314         return res_error_head;
 315       case MISCREG_QUEUE_RES_ERROR_TAIL:
 316         return res_error_tail;
 317       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 318         return nres_error_head;
 319       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 320         return nres_error_tail;
 321       default:
 322         panic("Miscellaneous register %d not implemented\n", miscReg);
 323     }
 324 }
 325
 326 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 327 {
 328     switch (miscReg) {
 329         // tick and stick are aliased to each other in niagra
 330         // well store the tick data in stick and the interrupt bit in tick
 331       case MISCREG_STICK:
 332       case MISCREG_TICK:
 333       case MISCREG_PRIVTICK:
 334         // I'm not sure why legion ignores the lowest two bits, but we'll go
 335         // with it
 336         // change from curCycle() to instCount() until we're done with legion
 337         DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
 338                 tc->getCpuPtr()->instCount(), stick);
 339         return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
 340                mbits(tick,63,63);
 341       case MISCREG_FPRS:
 342         // in legion if fp is enabled du and dl are set
 343         return fprs | 0x3;
 344       case MISCREG_PCR:
 345       case MISCREG_PIC:
 346         panic("Performance Instrumentation not impl\n");
 347       case MISCREG_SOFTINT_CLR:
 348       case MISCREG_SOFTINT_SET:
 349         panic("Can read from softint clr/set\n");
 350       case MISCREG_SOFTINT:
 351       case MISCREG_TICK_CMPR:
 352       case MISCREG_STICK_CMPR:
 353       case MISCREG_HINTP:
 354       case MISCREG_HTSTATE:
 355       case MISCREG_HTBA:
 356       case MISCREG_HVER:
 357       case MISCREG_STRAND_STS_REG:
 358       case MISCREG_HSTICK_CMPR:
 359       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 360       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 361       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 362       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 363       case MISCREG_QUEUE_RES_ERROR_HEAD:
 364       case MISCREG_QUEUE_RES_ERROR_TAIL:
 365       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 366       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 367 #if FULL_SYSTEM
 368       case MISCREG_HPSTATE:
 369         return readFSReg(miscReg, tc);
 370 #else
 371       case MISCREG_HPSTATE:
 372         //HPSTATE is special because because sometimes in privilege checks for instructions
 373         //it will read HPSTATE to make sure the priv. level is ok
 374         //So, we'll just have to tell it it isn't, instead of panicing.
 375         return 0;
 376
 377       panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
 378 #endif
 379
 380     }
 381     return readRegNoEffect(miscReg);
 382 }
 383
 384 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 385 {
 386     switch (miscReg) {
 387 //      case MISCREG_Y:
 388 //        y = val;
 389 //        break;
 390 //      case MISCREG_CCR:
 391 //        ccr = val;
 392 //        break;
 393       case MISCREG_ASI:
 394         asi = val;
 395         break;
 396       case MISCREG_FPRS:
 397         fprs = val;
 398         break;
 399       case MISCREG_TICK:
 400         tick = val;
 401         break;
 402       case MISCREG_PCR:
 403         panic("PCR not implemented\n");
 404       case MISCREG_PIC:
 405         panic("PIC not implemented\n");
 406       case MISCREG_GSR:
 407         gsr = val;
 408         break;
 409       case MISCREG_SOFTINT:
 410         softint = val;
 411         break;
 412       case MISCREG_TICK_CMPR:
 413         tick_cmpr = val;
 414         break;
 415       case MISCREG_STICK:
 416         stick = val;
 417         break;
 418       case MISCREG_STICK_CMPR:
 419         stick_cmpr = val;
 420         break;
 421
 422         /** Privilged Registers */
 423       case MISCREG_TPC:
 424         tpc[tl-1] = val;
 425         break;
 426       case MISCREG_TNPC:
 427         tnpc[tl-1] = val;
 428         break;
 429       case MISCREG_TSTATE:
 430         tstate[tl-1] = val;
 431         break;
 432       case MISCREG_TT:
 433         tt[tl-1] = val;
 434         break;
 435       case MISCREG_PRIVTICK:
 436         panic("Priviliged access to tick regesiters not implemented\n");
 437       case MISCREG_TBA:
 438         // clear lower 7 bits on writes.
 439         tba = val & ULL(~0x7FFF);
 440         break;
 441       case MISCREG_PSTATE:
 442         pstate = (val & PSTATE_MASK);
 443         break;
 444       case MISCREG_TL:
 445         tl = val;
 446         break;
 447       case MISCREG_PIL:
 448         pil = val;
 449         break;
 450       case MISCREG_CWP:
 451         cwp = val;
 452         break;
 453 //      case MISCREG_CANSAVE:
 454 //        cansave = val;
 455 //        break;
 456 //      case MISCREG_CANRESTORE:
 457 //        canrestore = val;
 458 //        break;
 459 //      case MISCREG_CLEANWIN:
 460 //        cleanwin = val;
 461 //        break;
 462 //      case MISCREG_OTHERWIN:
 463 //        otherwin = val;
 464 //        break;
 465 //      case MISCREG_WSTATE:
 466 //        wstate = val;
 467 //        break;
 468       case MISCREG_GL:
 469         gl = val;
 470         break;
 471
 472         /** Hyper privileged registers */
 473       case MISCREG_HPSTATE:
 474         hpstate = val;
 475         break;
 476       case MISCREG_HTSTATE:
 477         htstate[tl-1] = val;
 478         break;
 479       case MISCREG_HINTP:
 480         hintp = val;
 481       case MISCREG_HTBA:
 482         htba = val;
 483         break;
 484       case MISCREG_STRAND_STS_REG:
 485         strandStatusReg = val;
 486         break;
 487       case MISCREG_HSTICK_CMPR:
 488         hstick_cmpr = val;
 489         break;
 490
 491         /** Floating Point Status Register */
 492       case MISCREG_FSR:
 493         fsr = val;
 494         DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
 495         break;
 496
 497       case MISCREG_MMU_P_CONTEXT:
 498         priContext = val;
 499         break;
 500       case MISCREG_MMU_S_CONTEXT:
 501         secContext = val;
 502         break;
 503       case MISCREG_MMU_PART_ID:
 504         partId = val;
 505         break;
 506       case MISCREG_MMU_LSU_CTRL:
 507         lsuCtrlReg = val;
 508         break;
 509
 510       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 511         iTlbC0TsbPs0 = val;
 512         break;
 513       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 514         iTlbC0TsbPs1 = val;
 515         break;
 516       case MISCREG_MMU_ITLB_C0_CONFIG:
 517         iTlbC0Config = val;
 518         break;
 519       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 520         iTlbCXTsbPs0 = val;
 521         break;
 522       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 523         iTlbCXTsbPs1 = val;
 524         break;
 525       case MISCREG_MMU_ITLB_CX_CONFIG:
 526         iTlbCXConfig = val;
 527         break;
 528       case MISCREG_MMU_ITLB_SFSR:
 529         iTlbSfsr = val;
 530         break;
 531       case MISCREG_MMU_ITLB_TAG_ACCESS:
 532         iTlbTagAccess = val;
 533         break;
 534
 535       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 536         dTlbC0TsbPs0 = val;
 537         break;
 538       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 539         dTlbC0TsbPs1 = val;
 540         break;
 541       case MISCREG_MMU_DTLB_C0_CONFIG:
 542         dTlbC0Config = val;
 543         break;
 544       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 545         dTlbCXTsbPs0 = val;
 546         break;
 547       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 548         dTlbCXTsbPs1 = val;
 549         break;
 550       case MISCREG_MMU_DTLB_CX_CONFIG:
 551         dTlbCXConfig = val;
 552         break;
 553       case MISCREG_MMU_DTLB_SFSR:
 554         dTlbSfsr = val;
 555         break;
 556       case MISCREG_MMU_DTLB_SFAR:
 557         dTlbSfar = val;
 558         break;
 559       case MISCREG_MMU_DTLB_TAG_ACCESS:
 560         dTlbTagAccess = val;
 561         break;
 562
 563       case MISCREG_SCRATCHPAD_R0:
 564         scratchPad[0] = val;
 565         break;
 566       case MISCREG_SCRATCHPAD_R1:
 567         scratchPad[1] = val;
 568         break;
 569       case MISCREG_SCRATCHPAD_R2:
 570         scratchPad[2] = val;
 571         break;
 572       case MISCREG_SCRATCHPAD_R3:
 573         scratchPad[3] = val;
 574         break;
 575       case MISCREG_SCRATCHPAD_R4:
 576         scratchPad[4] = val;
 577         break;
 578       case MISCREG_SCRATCHPAD_R5:
 579         scratchPad[5] = val;
 580         break;
 581       case MISCREG_SCRATCHPAD_R6:
 582         scratchPad[6] = val;
 583         break;
 584       case MISCREG_SCRATCHPAD_R7:
 585         scratchPad[7] = val;
 586         break;
 587       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 588         cpu_mondo_head = val;
 589         break;
 590       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 591         cpu_mondo_tail = val;
 592         break;
 593       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 594         dev_mondo_head = val;
 595         break;
 596       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 597         dev_mondo_tail = val;
 598         break;
 599       case MISCREG_QUEUE_RES_ERROR_HEAD:
 600         res_error_head = val;
 601         break;
 602       case MISCREG_QUEUE_RES_ERROR_TAIL:
 603         res_error_tail = val;
 604         break;
 605       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 606         nres_error_head = val;
 607         break;
 608       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 609         nres_error_tail = val;
 610         break;
 611       default:
 612         panic("Miscellaneous register %d not implemented\n", miscReg);
 613     }
 614 }
 615
 616 void MiscRegFile::setReg(int miscReg,
 617         const MiscReg &val, ThreadContext * tc)
 618 {
 619     MiscReg new_val = val;
 620
 621     switch (miscReg) {
 622       case MISCREG_STICK:
 623       case MISCREG_TICK:
 624         // stick and tick are same thing on niagra
 625         // use stick for offset and tick for holding intrrupt bit
 626         stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
 627         tick = mbits(val,63,63);
 628         DPRINTF(Timer, "Writing TICK=%#X\n", val);
 629         break;
 630       case MISCREG_FPRS:
 631         //Configure the fpu based on the fprs
 632         break;
 633       case MISCREG_PCR:
 634         //Set up performance counting based on pcr value
 635         break;
 636       case MISCREG_PSTATE:
 637         pstate = val & PSTATE_MASK;
 638         return;
 639       case MISCREG_TL:
 640         tl = val;
 641 #if FULL_SYSTEM
 642         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
 643             tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
 644         else
 645             tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
 646 #endif
 647         return;
 648       case MISCREG_CWP:
 649         new_val = val >= NWindows ? NWindows - 1 : val;
 650         if (val >= NWindows)
 651             new_val = NWindows - 1;
 652
 653         tc->changeRegFileContext(CONTEXT_CWP, new_val);
 654         break;
 655       case MISCREG_GL:
 656         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 657         break;
 658       case MISCREG_PIL:
 659       case MISCREG_SOFTINT:
 660       case MISCREG_SOFTINT_SET:
 661       case MISCREG_SOFTINT_CLR:
 662       case MISCREG_TICK_CMPR:
 663       case MISCREG_STICK_CMPR:
 664       case MISCREG_HINTP:
 665       case MISCREG_HTSTATE:
 666       case MISCREG_HTBA:
 667       case MISCREG_HVER:
 668       case MISCREG_STRAND_STS_REG:
 669       case MISCREG_HSTICK_CMPR:
 670       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 671       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 672       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 673       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 674       case MISCREG_QUEUE_RES_ERROR_HEAD:
 675       case MISCREG_QUEUE_RES_ERROR_TAIL:
 676       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 677       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 678 #if FULL_SYSTEM
 679       case MISCREG_HPSTATE:
 680         setFSReg(miscReg, val, tc);
 681         return;
 682 #else
 683       case MISCREG_HPSTATE:
 684         //HPSTATE is special because normal trap processing saves HPSTATE when
 685         //it goes into a trap, and restores it when it returns.
 686         return;
 687       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 688 #endif
 689     }
 690     setRegNoEffect(miscReg, new_val);
 691 }
 692
 693 void MiscRegFile::serialize(std::ostream & os)
 694 {
 695     SERIALIZE_SCALAR(asi);
 696     SERIALIZE_SCALAR(tick);
 697     SERIALIZE_SCALAR(fprs);
 698     SERIALIZE_SCALAR(gsr);
 699     SERIALIZE_SCALAR(softint);
 700     SERIALIZE_SCALAR(tick_cmpr);
 701     SERIALIZE_SCALAR(stick);
 702     SERIALIZE_SCALAR(stick_cmpr);
 703     SERIALIZE_ARRAY(tpc,MaxTL);
 704     SERIALIZE_ARRAY(tnpc,MaxTL);
 705     SERIALIZE_ARRAY(tstate,MaxTL);
 706     SERIALIZE_ARRAY(tt,MaxTL);
 707     SERIALIZE_SCALAR(tba);
 708     SERIALIZE_SCALAR(pstate);
 709     SERIALIZE_SCALAR(tl);
 710     SERIALIZE_SCALAR(pil);
 711     SERIALIZE_SCALAR(cwp);
 712     SERIALIZE_SCALAR(gl);
 713     SERIALIZE_SCALAR(hpstate);
 714     SERIALIZE_ARRAY(htstate,MaxTL);
 715     SERIALIZE_SCALAR(hintp);
 716     SERIALIZE_SCALAR(htba);
 717     SERIALIZE_SCALAR(hstick_cmpr);
 718     SERIALIZE_SCALAR(strandStatusReg);
 719     SERIALIZE_SCALAR(fsr);
 720     SERIALIZE_SCALAR(priContext);
 721     SERIALIZE_SCALAR(secContext);
 722     SERIALIZE_SCALAR(partId);
 723     SERIALIZE_SCALAR(lsuCtrlReg);
 724     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 725     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 726     SERIALIZE_SCALAR(iTlbC0Config);
 727     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 728     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 729     SERIALIZE_SCALAR(iTlbCXConfig);
 730     SERIALIZE_SCALAR(iTlbSfsr);
 731     SERIALIZE_SCALAR(iTlbTagAccess);
 732     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 733     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 734     SERIALIZE_SCALAR(dTlbC0Config);
 735     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 736     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 737     SERIALIZE_SCALAR(dTlbCXConfig);
 738     SERIALIZE_SCALAR(dTlbSfsr);
 739     SERIALIZE_SCALAR(dTlbSfar);
 740     SERIALIZE_SCALAR(dTlbTagAccess);
 741     SERIALIZE_ARRAY(scratchPad,8);
 742     SERIALIZE_SCALAR(cpu_mondo_head);
 743     SERIALIZE_SCALAR(cpu_mondo_tail);
 744     SERIALIZE_SCALAR(dev_mondo_head);
 745     SERIALIZE_SCALAR(dev_mondo_tail);
 746     SERIALIZE_SCALAR(res_error_head);
 747     SERIALIZE_SCALAR(res_error_tail);
 748     SERIALIZE_SCALAR(nres_error_head);
 749     SERIALIZE_SCALAR(nres_error_tail);
 750 #if FULL_SYSTEM
 751     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 752     ThreadContext *tc = NULL;
 753     BaseCPU *cpu = NULL;
 754     int tc_num = 0;
 755     bool tick_intr_sched = true;
 756
 757     if (tickCompare)
 758         tc = tickCompare->getTC();
 759     else if (sTickCompare)
 760         tc = sTickCompare->getTC();
 761     else if (hSTickCompare)
 762         tc = hSTickCompare->getTC();
 763     else
 764         tick_intr_sched = false;
 765
 766     SERIALIZE_SCALAR(tick_intr_sched);
 767
 768     if (tc) {
 769         cpu = tc->getCpuPtr();
 770         tc_num = cpu->findContext(tc);
 771         if (tickCompare && tickCompare->scheduled())
 772             tick_cmp = tickCompare->when();
 773         if (sTickCompare && sTickCompare->scheduled())
 774             stick_cmp = sTickCompare->when();
 775         if (hSTickCompare && hSTickCompare->scheduled())
 776             hstick_cmp = hSTickCompare->when();
 777
 778         SERIALIZE_OBJPTR(cpu);
 779         SERIALIZE_SCALAR(tc_num);
 780         SERIALIZE_SCALAR(tick_cmp);
 781         SERIALIZE_SCALAR(stick_cmp);
 782         SERIALIZE_SCALAR(hstick_cmp);
 783     }
 784 #endif
 785 }
 786
 787 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 788 {
 789     UNSERIALIZE_SCALAR(asi);
 790     UNSERIALIZE_SCALAR(tick);
 791     UNSERIALIZE_SCALAR(fprs);
 792     UNSERIALIZE_SCALAR(gsr);
 793     UNSERIALIZE_SCALAR(softint);
 794     UNSERIALIZE_SCALAR(tick_cmpr);
 795     UNSERIALIZE_SCALAR(stick);
 796     UNSERIALIZE_SCALAR(stick_cmpr);
 797     UNSERIALIZE_ARRAY(tpc,MaxTL);
 798     UNSERIALIZE_ARRAY(tnpc,MaxTL);
 799     UNSERIALIZE_ARRAY(tstate,MaxTL);
 800     UNSERIALIZE_ARRAY(tt,MaxTL);
 801     UNSERIALIZE_SCALAR(tba);
 802     UNSERIALIZE_SCALAR(pstate);
 803     UNSERIALIZE_SCALAR(tl);
 804     UNSERIALIZE_SCALAR(pil);
 805     UNSERIALIZE_SCALAR(cwp);
 806     UNSERIALIZE_SCALAR(gl);
 807     UNSERIALIZE_SCALAR(hpstate);
 808     UNSERIALIZE_ARRAY(htstate,MaxTL);
 809     UNSERIALIZE_SCALAR(hintp);
 810     UNSERIALIZE_SCALAR(htba);
 811     UNSERIALIZE_SCALAR(hstick_cmpr);
 812     UNSERIALIZE_SCALAR(strandStatusReg);
 813     UNSERIALIZE_SCALAR(fsr);
 814     UNSERIALIZE_SCALAR(priContext);
 815     UNSERIALIZE_SCALAR(secContext);
 816     UNSERIALIZE_SCALAR(partId);
 817     UNSERIALIZE_SCALAR(lsuCtrlReg);
 818     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 819     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 820     UNSERIALIZE_SCALAR(iTlbC0Config);
 821     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 822     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 823     UNSERIALIZE_SCALAR(iTlbCXConfig);
 824     UNSERIALIZE_SCALAR(iTlbSfsr);
 825     UNSERIALIZE_SCALAR(iTlbTagAccess);
 826     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 827     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 828     UNSERIALIZE_SCALAR(dTlbC0Config);
 829     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 830     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 831     UNSERIALIZE_SCALAR(dTlbCXConfig);
 832     UNSERIALIZE_SCALAR(dTlbSfsr);
 833     UNSERIALIZE_SCALAR(dTlbSfar);
 834     UNSERIALIZE_SCALAR(dTlbTagAccess);
 835     UNSERIALIZE_ARRAY(scratchPad,8);
 836     UNSERIALIZE_SCALAR(cpu_mondo_head);
 837     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 838     UNSERIALIZE_SCALAR(dev_mondo_head);
 839     UNSERIALIZE_SCALAR(dev_mondo_tail);
 840     UNSERIALIZE_SCALAR(res_error_head);
 841     UNSERIALIZE_SCALAR(res_error_tail);
 842     UNSERIALIZE_SCALAR(nres_error_head);
 843     UNSERIALIZE_SCALAR(nres_error_tail);
 844
 845 #if FULL_SYSTEM
 846     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 847     ThreadContext *tc = NULL;
 848     BaseCPU *cpu = NULL;
 849     int tc_num;
 850     bool tick_intr_sched;
 851     UNSERIALIZE_SCALAR(tick_intr_sched);
 852     if (tick_intr_sched) {
 853         UNSERIALIZE_OBJPTR(cpu);
 854         if (cpu) {
 855             UNSERIALIZE_SCALAR(tc_num);
 856             UNSERIALIZE_SCALAR(tick_cmp);
 857             UNSERIALIZE_SCALAR(stick_cmp);
 858             UNSERIALIZE_SCALAR(hstick_cmp);
 859             tc = cpu->getContext(tc_num);
 860
 861             if (tick_cmp) {
 862                 tickCompare = new TickCompareEvent(this, tc);
 863                 tickCompare->schedule(tick_cmp);
 864             }
 865             if (stick_cmp)  {
 866                 sTickCompare = new STickCompareEvent(this, tc);
 867                 sTickCompare->schedule(stick_cmp);
 868             }
 869             if (hstick_cmp)  {
 870                 hSTickCompare = new HSTickCompareEvent(this, tc);
 871                 hSTickCompare->schedule(hstick_cmp);
 872             }
 873         }
 874     }
 875
 876  #endif
 877 }