src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49         {/*"y", "ccr",*/ "asi", "tick", "fprs", "pcr", "pic",
  50          "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51          "stick", "stick_cmpr",
  52          "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53          "pil", "cwp", /*"cansave", "canrestore", "cleanwin", "otherwin",
  54          "wstate",*/ "gl",
  55          "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56          "hstick_cmpr",
  57          "fsr", "prictx", "secctx", "partId", "lsuCtrlReg", "itbTsbC0Ps0",
  58          "itbTsbC0Ps1", "iTlbC0Cnfg", "itbTsbCXPs0", "itbTsbCXPs1",
  59          "iTlbCXCnfg","iTlbSfsr", "iTlbTagAcs", "dtbTsbC0Ps0",
  60          "dtbTsbC0Ps1", "dTlbC0Cnfg", "dtbTsbCXPs0", "dtbTsbCXPs1",
  61          "dTlbCXCnfg","dTlbSfsr", "dTlbSfar", "dTlbTagAcs",
  62          "scratch0", "scratch1", "scratch2", "scratch3", "scratch4",
  63          "scratch5", "scratch6", "scratch7", "cpuMondoHead", "cpuMondoTail",
  64          "devMondoHead", "devMondoTail", "resErrorHead", "resErrorTail",
  65          "nresErrorHead", "nresErrorTail", "TlbData" };
  66
  67     return miscRegName[index];
  68 }
  69
  70 enum RegMask
  71 {
  72         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  73 };
  74
  75 void MiscRegFile::clear()
  76 {
  77     //y = 0;
  78     //ccr = 0;
  79     asi = 0;
  80     tick = ULL(1) << 63;
  81     fprs = 0;
  82     gsr = 0;
  83     softint = 0;
  84     tick_cmpr = 0;
  85     stick = 0;
  86     stick_cmpr = 0;
  87     memset(tpc, 0, sizeof(tpc));
  88     memset(tnpc, 0, sizeof(tnpc));
  89     memset(tstate, 0, sizeof(tstate));
  90     memset(tt, 0, sizeof(tt));
  91     pstate = 0;
  92     tl = 0;
  93     pil = 0;
  94     cwp = 0;
  95     //cansave = 0;
  96     //canrestore = 0;
  97     //cleanwin = 0;
  98     //otherwin = 0;
  99     //wstate = 0;
 100     gl = 0;
 101     //In a T1, bit 11 is apparently always 1
 102     hpstate = (1 << 11);
 103     memset(htstate, 0, sizeof(htstate));
 104     hintp = 0;
 105     htba = 0;
 106     hstick_cmpr = 0;
 107     //This is set this way in Legion for some reason
 108     strandStatusReg = 0x50000;
 109     fsr = 0;
 110
 111     priContext = 0;
 112     secContext = 0;
 113     partId = 0;
 114     lsuCtrlReg = 0;
 115
 116     iTlbC0TsbPs0 = 0;
 117     iTlbC0TsbPs1 = 0;
 118     iTlbC0Config = 0;
 119     iTlbCXTsbPs0 = 0;
 120     iTlbCXTsbPs1 = 0;
 121     iTlbCXConfig = 0;
 122     iTlbSfsr = 0;
 123     iTlbTagAccess = 0;
 124
 125     dTlbC0TsbPs0 = 0;
 126     dTlbC0TsbPs1 = 0;
 127     dTlbC0Config = 0;
 128     dTlbCXTsbPs0 = 0;
 129     dTlbCXTsbPs1 = 0;
 130     dTlbCXConfig = 0;
 131     dTlbSfsr = 0;
 132     dTlbSfar = 0;
 133     dTlbTagAccess = 0;
 134
 135     memset(scratchPad, 0, sizeof(scratchPad));
 136 #if FULL_SYSTEM
 137     tickCompare = NULL;
 138     sTickCompare = NULL;
 139     hSTickCompare = NULL;
 140 #endif
 141 }
 142
 143 MiscReg MiscRegFile::readRegNoEffect(int miscReg)
 144 {
 145
 146   // The three miscRegs are moved up from the switch statement
 147   // due to more frequent calls.
 148
 149   if (miscReg == MISCREG_GL)
 150     return gl;
 151   if (miscReg == MISCREG_CWP)
 152     return cwp;
 153   if (miscReg == MISCREG_TLB_DATA) {
 154     /* Package up all the data for the tlb:
 155      * 6666555555555544444444443333333333222222222211111111110000000000
 156      * 3210987654321098765432109876543210987654321098765432109876543210
 157      *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
 158      *                                                           ||||^red
 159      *                                                           |||^priv
 160      *                                                           ||^am
 161      *                                                           |^lsuim
 162      *                                                           ^lsudm
 163      */
 164     return bits((uint64_t)hpstate,2,2) |
 165            bits((uint64_t)hpstate,5,5) << 1 |
 166            bits((uint64_t)pstate,3,2) << 2 |
 167            bits((uint64_t)lsuCtrlReg,3,2) << 4 |
 168            bits((uint64_t)partId,7,0) << 8 |
 169            bits((uint64_t)tl,2,0) << 16 |
 170                 (uint64_t)priContext << 32 |
 171                 (uint64_t)secContext << 48;
 172   }
 173
 174     switch (miscReg) {
 175       //case MISCREG_TLB_DATA:
 176       //  [original contents see above]
 177       //case MISCREG_Y:
 178       //  return y;
 179       //case MISCREG_CCR:
 180       //  return ccr;
 181       case MISCREG_ASI:
 182         return asi;
 183       case MISCREG_FPRS:
 184         return fprs;
 185       case MISCREG_TICK:
 186         return tick;
 187       case MISCREG_PCR:
 188         panic("PCR not implemented\n");
 189       case MISCREG_PIC:
 190         panic("PIC not implemented\n");
 191       case MISCREG_GSR:
 192         return gsr;
 193       case MISCREG_SOFTINT:
 194         return softint;
 195       case MISCREG_TICK_CMPR:
 196         return tick_cmpr;
 197       case MISCREG_STICK:
 198         return stick;
 199       case MISCREG_STICK_CMPR:
 200         return stick_cmpr;
 201
 202         /** Privilged Registers */
 203       case MISCREG_TPC:
 204         return tpc[tl-1];
 205       case MISCREG_TNPC:
 206         return tnpc[tl-1];
 207       case MISCREG_TSTATE:
 208         return tstate[tl-1];
 209       case MISCREG_TT:
 210         return tt[tl-1];
 211       case MISCREG_PRIVTICK:
 212         panic("Priviliged access to tick registers not implemented\n");
 213       case MISCREG_TBA:
 214         return tba;
 215       case MISCREG_PSTATE:
 216         return pstate;
 217       case MISCREG_TL:
 218         return tl;
 219       case MISCREG_PIL:
 220         return pil;
 221       //CWP, GL moved
 222       //case MISCREG_CWP:
 223       //  return cwp;
 224       //case MISCREG_CANSAVE:
 225       //  return cansave;
 226       //case MISCREG_CANRESTORE:
 227       //  return canrestore;
 228       //case MISCREG_CLEANWIN:
 229       //  return cleanwin;
 230       //case MISCREG_OTHERWIN:
 231       //  return otherwin;
 232       //case MISCREG_WSTATE:
 233       //  return wstate;
 234       //case MISCREG_GL:
 235       //  return gl;
 236
 237         /** Hyper privileged registers */
 238       case MISCREG_HPSTATE:
 239         return hpstate;
 240       case MISCREG_HTSTATE:
 241         return htstate[tl-1];
 242       case MISCREG_HINTP:
 243         return hintp;
 244       case MISCREG_HTBA:
 245         return htba;
 246       case MISCREG_STRAND_STS_REG:
 247         return strandStatusReg;
 248       case MISCREG_HSTICK_CMPR:
 249         return hstick_cmpr;
 250
 251         /** Floating Point Status Register */
 252       case MISCREG_FSR:
 253         DPRINTF(Sparc, "FSR read as: %#x\n", fsr);
 254         return fsr;
 255
 256       case MISCREG_MMU_P_CONTEXT:
 257         return priContext;
 258       case MISCREG_MMU_S_CONTEXT:
 259         return secContext;
 260       case MISCREG_MMU_PART_ID:
 261         return partId;
 262       case MISCREG_MMU_LSU_CTRL:
 263         return lsuCtrlReg;
 264
 265       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 266         return iTlbC0TsbPs0;
 267       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 268         return iTlbC0TsbPs1;
 269       case MISCREG_MMU_ITLB_C0_CONFIG:
 270         return iTlbC0Config;
 271       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 272         return iTlbCXTsbPs0;
 273       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 274         return iTlbCXTsbPs1;
 275       case MISCREG_MMU_ITLB_CX_CONFIG:
 276         return iTlbCXConfig;
 277       case MISCREG_MMU_ITLB_SFSR:
 278         return iTlbSfsr;
 279       case MISCREG_MMU_ITLB_TAG_ACCESS:
 280         return iTlbTagAccess;
 281
 282       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 283         return dTlbC0TsbPs0;
 284       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 285         return dTlbC0TsbPs1;
 286       case MISCREG_MMU_DTLB_C0_CONFIG:
 287         return dTlbC0Config;
 288       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 289         return dTlbCXTsbPs0;
 290       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 291         return dTlbCXTsbPs1;
 292       case MISCREG_MMU_DTLB_CX_CONFIG:
 293         return dTlbCXConfig;
 294       case MISCREG_MMU_DTLB_SFSR:
 295         return dTlbSfsr;
 296       case MISCREG_MMU_DTLB_SFAR:
 297         return dTlbSfar;
 298       case MISCREG_MMU_DTLB_TAG_ACCESS:
 299         return dTlbTagAccess;
 300
 301       case MISCREG_SCRATCHPAD_R0:
 302         return scratchPad[0];
 303       case MISCREG_SCRATCHPAD_R1:
 304         return scratchPad[1];
 305       case MISCREG_SCRATCHPAD_R2:
 306         return scratchPad[2];
 307       case MISCREG_SCRATCHPAD_R3:
 308         return scratchPad[3];
 309       case MISCREG_SCRATCHPAD_R4:
 310         return scratchPad[4];
 311       case MISCREG_SCRATCHPAD_R5:
 312         return scratchPad[5];
 313       case MISCREG_SCRATCHPAD_R6:
 314         return scratchPad[6];
 315       case MISCREG_SCRATCHPAD_R7:
 316         return scratchPad[7];
 317       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 318         return cpu_mondo_head;
 319       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 320         return cpu_mondo_tail;
 321       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 322         return dev_mondo_head;
 323       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 324         return dev_mondo_tail;
 325       case MISCREG_QUEUE_RES_ERROR_HEAD:
 326         return res_error_head;
 327       case MISCREG_QUEUE_RES_ERROR_TAIL:
 328         return res_error_tail;
 329       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 330         return nres_error_head;
 331       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 332         return nres_error_tail;
 333       default:
 334         panic("Miscellaneous register %d not implemented\n", miscReg);
 335     }
 336 }
 337
 338 MiscReg MiscRegFile::readReg(int miscReg, ThreadContext * tc)
 339 {
 340     switch (miscReg) {
 341         // tick and stick are aliased to each other in niagra
 342         // well store the tick data in stick and the interrupt bit in tick
 343       case MISCREG_STICK:
 344       case MISCREG_TICK:
 345       case MISCREG_PRIVTICK:
 346         // I'm not sure why legion ignores the lowest two bits, but we'll go
 347         // with it
 348         // change from curCycle() to instCount() until we're done with legion
 349         DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
 350                 tc->getCpuPtr()->instCount(), stick);
 351         return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
 352                mbits(tick,63,63);
 353       case MISCREG_FPRS:
 354         // in legion if fp is enabled du and dl are set
 355         return fprs | 0x3;
 356       case MISCREG_PCR:
 357       case MISCREG_PIC:
 358         panic("Performance Instrumentation not impl\n");
 359       case MISCREG_SOFTINT_CLR:
 360       case MISCREG_SOFTINT_SET:
 361         panic("Can read from softint clr/set\n");
 362       case MISCREG_SOFTINT:
 363       case MISCREG_TICK_CMPR:
 364       case MISCREG_STICK_CMPR:
 365       case MISCREG_HINTP:
 366       case MISCREG_HTSTATE:
 367       case MISCREG_HTBA:
 368       case MISCREG_HVER:
 369       case MISCREG_STRAND_STS_REG:
 370       case MISCREG_HSTICK_CMPR:
 371       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 372       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 373       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 374       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 375       case MISCREG_QUEUE_RES_ERROR_HEAD:
 376       case MISCREG_QUEUE_RES_ERROR_TAIL:
 377       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 378       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 379 #if FULL_SYSTEM
 380       case MISCREG_HPSTATE:
 381         return readFSReg(miscReg, tc);
 382 #else
 383       case MISCREG_HPSTATE:
 384         //HPSTATE is special because because sometimes in privilege checks for instructions
 385         //it will read HPSTATE to make sure the priv. level is ok
 386         //So, we'll just have to tell it it isn't, instead of panicing.
 387         return 0;
 388
 389       panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
 390 #endif
 391
 392     }
 393     return readRegNoEffect(miscReg);
 394 }
 395
 396 void MiscRegFile::setRegNoEffect(int miscReg, const MiscReg &val)
 397 {
 398     switch (miscReg) {
 399 //      case MISCREG_Y:
 400 //        y = val;
 401 //        break;
 402 //      case MISCREG_CCR:
 403 //        ccr = val;
 404 //        break;
 405       case MISCREG_ASI:
 406         asi = val;
 407         break;
 408       case MISCREG_FPRS:
 409         fprs = val;
 410         break;
 411       case MISCREG_TICK:
 412         tick = val;
 413         break;
 414       case MISCREG_PCR:
 415         panic("PCR not implemented\n");
 416       case MISCREG_PIC:
 417         panic("PIC not implemented\n");
 418       case MISCREG_GSR:
 419         gsr = val;
 420         break;
 421       case MISCREG_SOFTINT:
 422         softint = val;
 423         break;
 424       case MISCREG_TICK_CMPR:
 425         tick_cmpr = val;
 426         break;
 427       case MISCREG_STICK:
 428         stick = val;
 429         break;
 430       case MISCREG_STICK_CMPR:
 431         stick_cmpr = val;
 432         break;
 433
 434         /** Privilged Registers */
 435       case MISCREG_TPC:
 436         tpc[tl-1] = val;
 437         break;
 438       case MISCREG_TNPC:
 439         tnpc[tl-1] = val;
 440         break;
 441       case MISCREG_TSTATE:
 442         tstate[tl-1] = val;
 443         break;
 444       case MISCREG_TT:
 445         tt[tl-1] = val;
 446         break;
 447       case MISCREG_PRIVTICK:
 448         panic("Priviliged access to tick regesiters not implemented\n");
 449       case MISCREG_TBA:
 450         // clear lower 7 bits on writes.
 451         tba = val & ULL(~0x7FFF);
 452         break;
 453       case MISCREG_PSTATE:
 454         pstate = (val & PSTATE_MASK);
 455         break;
 456       case MISCREG_TL:
 457         tl = val;
 458         break;
 459       case MISCREG_PIL:
 460         pil = val;
 461         break;
 462       case MISCREG_CWP:
 463         cwp = val;
 464         break;
 465 //      case MISCREG_CANSAVE:
 466 //        cansave = val;
 467 //        break;
 468 //      case MISCREG_CANRESTORE:
 469 //        canrestore = val;
 470 //        break;
 471 //      case MISCREG_CLEANWIN:
 472 //        cleanwin = val;
 473 //        break;
 474 //      case MISCREG_OTHERWIN:
 475 //        otherwin = val;
 476 //        break;
 477 //      case MISCREG_WSTATE:
 478 //        wstate = val;
 479 //        break;
 480       case MISCREG_GL:
 481         gl = val;
 482         break;
 483
 484         /** Hyper privileged registers */
 485       case MISCREG_HPSTATE:
 486         hpstate = val;
 487         break;
 488       case MISCREG_HTSTATE:
 489         htstate[tl-1] = val;
 490         break;
 491       case MISCREG_HINTP:
 492         hintp = val;
 493       case MISCREG_HTBA:
 494         htba = val;
 495         break;
 496       case MISCREG_STRAND_STS_REG:
 497         strandStatusReg = val;
 498         break;
 499       case MISCREG_HSTICK_CMPR:
 500         hstick_cmpr = val;
 501         break;
 502
 503         /** Floating Point Status Register */
 504       case MISCREG_FSR:
 505         fsr = val;
 506         DPRINTF(Sparc, "FSR written with: %#x\n", fsr);
 507         break;
 508
 509       case MISCREG_MMU_P_CONTEXT:
 510         priContext = val;
 511         break;
 512       case MISCREG_MMU_S_CONTEXT:
 513         secContext = val;
 514         break;
 515       case MISCREG_MMU_PART_ID:
 516         partId = val;
 517         break;
 518       case MISCREG_MMU_LSU_CTRL:
 519         lsuCtrlReg = val;
 520         break;
 521
 522       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 523         iTlbC0TsbPs0 = val;
 524         break;
 525       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 526         iTlbC0TsbPs1 = val;
 527         break;
 528       case MISCREG_MMU_ITLB_C0_CONFIG:
 529         iTlbC0Config = val;
 530         break;
 531       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 532         iTlbCXTsbPs0 = val;
 533         break;
 534       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 535         iTlbCXTsbPs1 = val;
 536         break;
 537       case MISCREG_MMU_ITLB_CX_CONFIG:
 538         iTlbCXConfig = val;
 539         break;
 540       case MISCREG_MMU_ITLB_SFSR:
 541         iTlbSfsr = val;
 542         break;
 543       case MISCREG_MMU_ITLB_TAG_ACCESS:
 544         iTlbTagAccess = val;
 545         break;
 546
 547       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 548         dTlbC0TsbPs0 = val;
 549         break;
 550       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 551         dTlbC0TsbPs1 = val;
 552         break;
 553       case MISCREG_MMU_DTLB_C0_CONFIG:
 554         dTlbC0Config = val;
 555         break;
 556       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 557         dTlbCXTsbPs0 = val;
 558         break;
 559       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 560         dTlbCXTsbPs1 = val;
 561         break;
 562       case MISCREG_MMU_DTLB_CX_CONFIG:
 563         dTlbCXConfig = val;
 564         break;
 565       case MISCREG_MMU_DTLB_SFSR:
 566         dTlbSfsr = val;
 567         break;
 568       case MISCREG_MMU_DTLB_SFAR:
 569         dTlbSfar = val;
 570         break;
 571       case MISCREG_MMU_DTLB_TAG_ACCESS:
 572         dTlbTagAccess = val;
 573         break;
 574
 575       case MISCREG_SCRATCHPAD_R0:
 576         scratchPad[0] = val;
 577         break;
 578       case MISCREG_SCRATCHPAD_R1:
 579         scratchPad[1] = val;
 580         break;
 581       case MISCREG_SCRATCHPAD_R2:
 582         scratchPad[2] = val;
 583         break;
 584       case MISCREG_SCRATCHPAD_R3:
 585         scratchPad[3] = val;
 586         break;
 587       case MISCREG_SCRATCHPAD_R4:
 588         scratchPad[4] = val;
 589         break;
 590       case MISCREG_SCRATCHPAD_R5:
 591         scratchPad[5] = val;
 592         break;
 593       case MISCREG_SCRATCHPAD_R6:
 594         scratchPad[6] = val;
 595         break;
 596       case MISCREG_SCRATCHPAD_R7:
 597         scratchPad[7] = val;
 598         break;
 599       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 600         cpu_mondo_head = val;
 601         break;
 602       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 603         cpu_mondo_tail = val;
 604         break;
 605       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 606         dev_mondo_head = val;
 607         break;
 608       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 609         dev_mondo_tail = val;
 610         break;
 611       case MISCREG_QUEUE_RES_ERROR_HEAD:
 612         res_error_head = val;
 613         break;
 614       case MISCREG_QUEUE_RES_ERROR_TAIL:
 615         res_error_tail = val;
 616         break;
 617       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 618         nres_error_head = val;
 619         break;
 620       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 621         nres_error_tail = val;
 622         break;
 623       default:
 624         panic("Miscellaneous register %d not implemented\n", miscReg);
 625     }
 626 }
 627
 628 void MiscRegFile::setReg(int miscReg,
 629         const MiscReg &val, ThreadContext * tc)
 630 {
 631     MiscReg new_val = val;
 632
 633     switch (miscReg) {
 634       case MISCREG_STICK:
 635       case MISCREG_TICK:
 636         // stick and tick are same thing on niagra
 637         // use stick for offset and tick for holding intrrupt bit
 638         stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
 639         tick = mbits(val,63,63);
 640         DPRINTF(Timer, "Writing TICK=%#X\n", val);
 641         break;
 642       case MISCREG_FPRS:
 643         //Configure the fpu based on the fprs
 644         break;
 645       case MISCREG_PCR:
 646         //Set up performance counting based on pcr value
 647         break;
 648       case MISCREG_PSTATE:
 649         pstate = val & PSTATE_MASK;
 650         return;
 651       case MISCREG_TL:
 652         tl = val;
 653 #if FULL_SYSTEM
 654         if (hpstate & HPSTATE::tlz && tl == 0 && !(hpstate & HPSTATE::hpriv))
 655             tc->getCpuPtr()->post_interrupt(IT_TRAP_LEVEL_ZERO,0);
 656         else
 657             tc->getCpuPtr()->clear_interrupt(IT_TRAP_LEVEL_ZERO,0);
 658 #endif
 659         return;
 660       case MISCREG_CWP:
 661         new_val = val >= NWindows ? NWindows - 1 : val;
 662         if (val >= NWindows)
 663             new_val = NWindows - 1;
 664
 665         tc->changeRegFileContext(CONTEXT_CWP, new_val);
 666         break;
 667       case MISCREG_GL:
 668         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 669         break;
 670       case MISCREG_PIL:
 671       case MISCREG_SOFTINT:
 672       case MISCREG_SOFTINT_SET:
 673       case MISCREG_SOFTINT_CLR:
 674       case MISCREG_TICK_CMPR:
 675       case MISCREG_STICK_CMPR:
 676       case MISCREG_HINTP:
 677       case MISCREG_HTSTATE:
 678       case MISCREG_HTBA:
 679       case MISCREG_HVER:
 680       case MISCREG_STRAND_STS_REG:
 681       case MISCREG_HSTICK_CMPR:
 682       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 683       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 684       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 685       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 686       case MISCREG_QUEUE_RES_ERROR_HEAD:
 687       case MISCREG_QUEUE_RES_ERROR_TAIL:
 688       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 689       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 690 #if FULL_SYSTEM
 691       case MISCREG_HPSTATE:
 692         setFSReg(miscReg, val, tc);
 693         return;
 694 #else
 695       case MISCREG_HPSTATE:
 696         //HPSTATE is special because normal trap processing saves HPSTATE when
 697         //it goes into a trap, and restores it when it returns.
 698         return;
 699       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 700 #endif
 701     }
 702     setRegNoEffect(miscReg, new_val);
 703 }
 704
 705 void MiscRegFile::serialize(std::ostream & os)
 706 {
 707     SERIALIZE_SCALAR(asi);
 708     SERIALIZE_SCALAR(tick);
 709     SERIALIZE_SCALAR(fprs);
 710     SERIALIZE_SCALAR(gsr);
 711     SERIALIZE_SCALAR(softint);
 712     SERIALIZE_SCALAR(tick_cmpr);
 713     SERIALIZE_SCALAR(stick);
 714     SERIALIZE_SCALAR(stick_cmpr);
 715     SERIALIZE_ARRAY(tpc,MaxTL);
 716     SERIALIZE_ARRAY(tnpc,MaxTL);
 717     SERIALIZE_ARRAY(tstate,MaxTL);
 718     SERIALIZE_ARRAY(tt,MaxTL);
 719     SERIALIZE_SCALAR(tba);
 720     SERIALIZE_SCALAR(pstate);
 721     SERIALIZE_SCALAR(tl);
 722     SERIALIZE_SCALAR(pil);
 723     SERIALIZE_SCALAR(cwp);
 724     SERIALIZE_SCALAR(gl);
 725     SERIALIZE_SCALAR(hpstate);
 726     SERIALIZE_ARRAY(htstate,MaxTL);
 727     SERIALIZE_SCALAR(hintp);
 728     SERIALIZE_SCALAR(htba);
 729     SERIALIZE_SCALAR(hstick_cmpr);
 730     SERIALIZE_SCALAR(strandStatusReg);
 731     SERIALIZE_SCALAR(fsr);
 732     SERIALIZE_SCALAR(priContext);
 733     SERIALIZE_SCALAR(secContext);
 734     SERIALIZE_SCALAR(partId);
 735     SERIALIZE_SCALAR(lsuCtrlReg);
 736     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 737     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 738     SERIALIZE_SCALAR(iTlbC0Config);
 739     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 740     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 741     SERIALIZE_SCALAR(iTlbCXConfig);
 742     SERIALIZE_SCALAR(iTlbSfsr);
 743     SERIALIZE_SCALAR(iTlbTagAccess);
 744     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 745     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 746     SERIALIZE_SCALAR(dTlbC0Config);
 747     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 748     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 749     SERIALIZE_SCALAR(dTlbCXConfig);
 750     SERIALIZE_SCALAR(dTlbSfsr);
 751     SERIALIZE_SCALAR(dTlbSfar);
 752     SERIALIZE_SCALAR(dTlbTagAccess);
 753     SERIALIZE_ARRAY(scratchPad,8);
 754     SERIALIZE_SCALAR(cpu_mondo_head);
 755     SERIALIZE_SCALAR(cpu_mondo_tail);
 756     SERIALIZE_SCALAR(dev_mondo_head);
 757     SERIALIZE_SCALAR(dev_mondo_tail);
 758     SERIALIZE_SCALAR(res_error_head);
 759     SERIALIZE_SCALAR(res_error_tail);
 760     SERIALIZE_SCALAR(nres_error_head);
 761     SERIALIZE_SCALAR(nres_error_tail);
 762 #if FULL_SYSTEM
 763     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 764     ThreadContext *tc = NULL;
 765     BaseCPU *cpu = NULL;
 766     int tc_num = 0;
 767     bool tick_intr_sched = true;
 768
 769     if (tickCompare)
 770         tc = tickCompare->getTC();
 771     else if (sTickCompare)
 772         tc = sTickCompare->getTC();
 773     else if (hSTickCompare)
 774         tc = hSTickCompare->getTC();
 775     else
 776         tick_intr_sched = false;
 777
 778     SERIALIZE_SCALAR(tick_intr_sched);
 779
 780     if (tc) {
 781         cpu = tc->getCpuPtr();
 782         tc_num = cpu->findContext(tc);
 783         if (tickCompare && tickCompare->scheduled())
 784             tick_cmp = tickCompare->when();
 785         if (sTickCompare && sTickCompare->scheduled())
 786             stick_cmp = sTickCompare->when();
 787         if (hSTickCompare && hSTickCompare->scheduled())
 788             hstick_cmp = hSTickCompare->when();
 789
 790         SERIALIZE_OBJPTR(cpu);
 791         SERIALIZE_SCALAR(tc_num);
 792         SERIALIZE_SCALAR(tick_cmp);
 793         SERIALIZE_SCALAR(stick_cmp);
 794         SERIALIZE_SCALAR(hstick_cmp);
 795     }
 796 #endif
 797 }
 798
 799 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 800 {
 801     UNSERIALIZE_SCALAR(asi);
 802     UNSERIALIZE_SCALAR(tick);
 803     UNSERIALIZE_SCALAR(fprs);
 804     UNSERIALIZE_SCALAR(gsr);
 805     UNSERIALIZE_SCALAR(softint);
 806     UNSERIALIZE_SCALAR(tick_cmpr);
 807     UNSERIALIZE_SCALAR(stick);
 808     UNSERIALIZE_SCALAR(stick_cmpr);
 809     UNSERIALIZE_ARRAY(tpc,MaxTL);
 810     UNSERIALIZE_ARRAY(tnpc,MaxTL);
 811     UNSERIALIZE_ARRAY(tstate,MaxTL);
 812     UNSERIALIZE_ARRAY(tt,MaxTL);
 813     UNSERIALIZE_SCALAR(tba);
 814     UNSERIALIZE_SCALAR(pstate);
 815     UNSERIALIZE_SCALAR(tl);
 816     UNSERIALIZE_SCALAR(pil);
 817     UNSERIALIZE_SCALAR(cwp);
 818     UNSERIALIZE_SCALAR(gl);
 819     UNSERIALIZE_SCALAR(hpstate);
 820     UNSERIALIZE_ARRAY(htstate,MaxTL);
 821     UNSERIALIZE_SCALAR(hintp);
 822     UNSERIALIZE_SCALAR(htba);
 823     UNSERIALIZE_SCALAR(hstick_cmpr);
 824     UNSERIALIZE_SCALAR(strandStatusReg);
 825     UNSERIALIZE_SCALAR(fsr);
 826     UNSERIALIZE_SCALAR(priContext);
 827     UNSERIALIZE_SCALAR(secContext);
 828     UNSERIALIZE_SCALAR(partId);
 829     UNSERIALIZE_SCALAR(lsuCtrlReg);
 830     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 831     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 832     UNSERIALIZE_SCALAR(iTlbC0Config);
 833     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 834     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 835     UNSERIALIZE_SCALAR(iTlbCXConfig);
 836     UNSERIALIZE_SCALAR(iTlbSfsr);
 837     UNSERIALIZE_SCALAR(iTlbTagAccess);
 838     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 839     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 840     UNSERIALIZE_SCALAR(dTlbC0Config);
 841     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 842     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 843     UNSERIALIZE_SCALAR(dTlbCXConfig);
 844     UNSERIALIZE_SCALAR(dTlbSfsr);
 845     UNSERIALIZE_SCALAR(dTlbSfar);
 846     UNSERIALIZE_SCALAR(dTlbTagAccess);
 847     UNSERIALIZE_ARRAY(scratchPad,8);
 848     UNSERIALIZE_SCALAR(cpu_mondo_head);
 849     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 850     UNSERIALIZE_SCALAR(dev_mondo_head);
 851     UNSERIALIZE_SCALAR(dev_mondo_tail);
 852     UNSERIALIZE_SCALAR(res_error_head);
 853     UNSERIALIZE_SCALAR(res_error_tail);
 854     UNSERIALIZE_SCALAR(nres_error_head);
 855     UNSERIALIZE_SCALAR(nres_error_tail);
 856
 857 #if FULL_SYSTEM
 858     Tick tick_cmp = 0, stick_cmp = 0, hstick_cmp = 0;
 859     ThreadContext *tc = NULL;
 860     BaseCPU *cpu = NULL;
 861     int tc_num;
 862     bool tick_intr_sched;
 863     UNSERIALIZE_SCALAR(tick_intr_sched);
 864     if (tick_intr_sched) {
 865         UNSERIALIZE_OBJPTR(cpu);
 866         if (cpu) {
 867             UNSERIALIZE_SCALAR(tc_num);
 868             UNSERIALIZE_SCALAR(tick_cmp);
 869             UNSERIALIZE_SCALAR(stick_cmp);
 870             UNSERIALIZE_SCALAR(hstick_cmp);
 871             tc = cpu->getContext(tc_num);
 872
 873             if (tick_cmp) {
 874                 tickCompare = new TickCompareEvent(this, tc);
 875                 tickCompare->schedule(tick_cmp);
 876             }
 877             if (stick_cmp)  {
 878                 sTickCompare = new STickCompareEvent(this, tc);
 879                 sTickCompare->schedule(stick_cmp);
 880             }
 881             if (hstick_cmp)  {
 882                 hSTickCompare = new HSTickCompareEvent(this, tc);
 883                 hSTickCompare->schedule(hstick_cmp);
 884             }
 885         }
 886     }
 887
 888  #endif
 889 }