src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49        {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
  50         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51         "stick", "stick_cmpr",
  52         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53         "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  54         "wstate", "gl",
  55         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56         "hstick_cmpr",
  57         "fsr"};
  58     return miscRegName[index];
  59 }
  60
  61 enum RegMask
  62 {
  63         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  64 };
  65
  66 void MiscRegFile::clear()
  67 {
  68     y = 0;
  69     ccr = 0;
  70     asi = 0;
  71     tick = ULL(1) << 63;
  72     fprs = 0;
  73     gsr = 0;
  74     softint = 0;
  75     tick_cmpr = 0;
  76     stick = 0;
  77     stick_cmpr = 0;
  78     memset(tpc, 0, sizeof(tpc));
  79     memset(tnpc, 0, sizeof(tnpc));
  80     memset(tstate, 0, sizeof(tstate));
  81     memset(tt, 0, sizeof(tt));
  82     pstate = 0;
  83     tl = 0;
  84     pil = 0;
  85     cwp = 0;
  86     cansave = 0;
  87     canrestore = 0;
  88     cleanwin = 0;
  89     otherwin = 0;
  90     wstate = 0;
  91     gl = 0;
  92     //In a T1, bit 11 is apparently always 1
  93     hpstate = (1 << 11);
  94     memset(htstate, 0, sizeof(htstate));
  95     hintp = 0;
  96     htba = 0;
  97     hstick_cmpr = 0;
  98     //This is set this way in Legion for some reason
  99     strandStatusReg = 0x50000;
 100     fsr = 0;
 101
 102     priContext = 0;
 103     secContext = 0;
 104     partId = 0;
 105     lsuCtrlReg = 0;
 106
 107     iTlbC0TsbPs0 = 0;
 108     iTlbC0TsbPs1 = 0;
 109     iTlbC0Config = 0;
 110     iTlbCXTsbPs0 = 0;
 111     iTlbCXTsbPs1 = 0;
 112     iTlbCXConfig = 0;
 113     iTlbSfsr = 0;
 114     iTlbTagAccess = 0;
 115
 116     dTlbC0TsbPs0 = 0;
 117     dTlbC0TsbPs1 = 0;
 118     dTlbC0Config = 0;
 119     dTlbCXTsbPs0 = 0;
 120     dTlbCXTsbPs1 = 0;
 121     dTlbCXConfig = 0;
 122     dTlbSfsr = 0;
 123     dTlbSfar = 0;
 124     dTlbTagAccess = 0;
 125
 126     memset(scratchPad, 0, sizeof(scratchPad));
 127 }
 128
 129 MiscReg MiscRegFile::readReg(int miscReg)
 130 {
 131     switch (miscReg) {
 132       case MISCREG_Y:
 133         return y;
 134       case MISCREG_CCR:
 135         return ccr;
 136       case MISCREG_ASI:
 137         return asi;
 138       case MISCREG_FPRS:
 139         return fprs;
 140       case MISCREG_TICK:
 141         return tick;
 142       case MISCREG_PCR:
 143         panic("PCR not implemented\n");
 144       case MISCREG_PIC:
 145         panic("PIC not implemented\n");
 146       case MISCREG_GSR:
 147         return gsr;
 148       case MISCREG_SOFTINT:
 149         return softint;
 150       case MISCREG_TICK_CMPR:
 151         return tick_cmpr;
 152       case MISCREG_STICK:
 153         return stick;
 154       case MISCREG_STICK_CMPR:
 155         return stick_cmpr;
 156
 157         /** Privilged Registers */
 158       case MISCREG_TPC:
 159         return tpc[tl-1];
 160       case MISCREG_TNPC:
 161         return tnpc[tl-1];
 162       case MISCREG_TSTATE:
 163         return tstate[tl-1];
 164       case MISCREG_TT:
 165         return tt[tl-1];
 166       case MISCREG_PRIVTICK:
 167         panic("Priviliged access to tick registers not implemented\n");
 168       case MISCREG_TBA:
 169         return tba;
 170       case MISCREG_PSTATE:
 171         return pstate;
 172       case MISCREG_TL:
 173         return tl;
 174       case MISCREG_PIL:
 175         return pil;
 176       case MISCREG_CWP:
 177         return cwp;
 178       case MISCREG_CANSAVE:
 179         return cansave;
 180       case MISCREG_CANRESTORE:
 181         return canrestore;
 182       case MISCREG_CLEANWIN:
 183         return cleanwin;
 184       case MISCREG_OTHERWIN:
 185         return otherwin;
 186       case MISCREG_WSTATE:
 187         return wstate;
 188       case MISCREG_GL:
 189         return gl;
 190
 191         /** Hyper privileged registers */
 192       case MISCREG_HPSTATE:
 193         return hpstate;
 194       case MISCREG_HTSTATE:
 195         return htstate[tl-1];
 196       case MISCREG_HINTP:
 197         panic("HINTP not implemented\n");
 198       case MISCREG_HTBA:
 199         return htba;
 200       case MISCREG_HVER:
 201         return NWindows | MaxTL << 8 | MaxGL << 16;
 202       case MISCREG_STRAND_STS_REG:
 203         return strandStatusReg;
 204       case MISCREG_HSTICK_CMPR:
 205         return hstick_cmpr;
 206
 207         /** Floating Point Status Register */
 208       case MISCREG_FSR:
 209         return fsr;
 210
 211       case MISCREG_MMU_P_CONTEXT:
 212         return priContext;
 213       case MISCREG_MMU_S_CONTEXT:
 214         return secContext;
 215       case MISCREG_MMU_PART_ID:
 216         return partId;
 217       case MISCREG_MMU_LSU_CTRL:
 218         return lsuCtrlReg;
 219
 220       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 221         return iTlbC0TsbPs0;
 222       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 223         return iTlbC0TsbPs1;
 224       case MISCREG_MMU_ITLB_C0_CONFIG:
 225         return iTlbC0Config;
 226       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 227         return iTlbCXTsbPs0;
 228       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 229         return iTlbCXTsbPs1;
 230       case MISCREG_MMU_ITLB_CX_CONFIG:
 231         return iTlbCXConfig;
 232       case MISCREG_MMU_ITLB_SFSR:
 233         return iTlbSfsr;
 234       case MISCREG_MMU_ITLB_TAG_ACCESS:
 235         return iTlbTagAccess;
 236
 237       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 238         return dTlbC0TsbPs0;
 239       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 240         return dTlbC0TsbPs1;
 241       case MISCREG_MMU_DTLB_C0_CONFIG:
 242         return dTlbC0Config;
 243       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 244         return dTlbCXTsbPs0;
 245       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 246         return dTlbCXTsbPs1;
 247       case MISCREG_MMU_DTLB_CX_CONFIG:
 248         return dTlbCXConfig;
 249       case MISCREG_MMU_DTLB_SFSR:
 250         return dTlbSfsr;
 251       case MISCREG_MMU_DTLB_SFAR:
 252         return dTlbSfar;
 253       case MISCREG_MMU_DTLB_TAG_ACCESS:
 254         return dTlbTagAccess;
 255
 256       case MISCREG_SCRATCHPAD_R0:
 257         return scratchPad[0];
 258       case MISCREG_SCRATCHPAD_R1:
 259         return scratchPad[1];
 260       case MISCREG_SCRATCHPAD_R2:
 261         return scratchPad[2];
 262       case MISCREG_SCRATCHPAD_R3:
 263         return scratchPad[3];
 264       case MISCREG_SCRATCHPAD_R4:
 265         return scratchPad[4];
 266       case MISCREG_SCRATCHPAD_R5:
 267         return scratchPad[5];
 268       case MISCREG_SCRATCHPAD_R6:
 269         return scratchPad[6];
 270       case MISCREG_SCRATCHPAD_R7:
 271         return scratchPad[7];
 272       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 273         return cpu_mondo_head;
 274       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 275         return cpu_mondo_tail;
 276       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 277         return dev_mondo_head;
 278       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 279         return dev_mondo_tail;
 280       case MISCREG_QUEUE_RES_ERROR_HEAD:
 281         return res_error_head;
 282       case MISCREG_QUEUE_RES_ERROR_TAIL:
 283         return res_error_tail;
 284       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 285         return nres_error_head;
 286       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 287         return nres_error_tail;
 288       default:
 289         panic("Miscellaneous register %d not implemented\n", miscReg);
 290     }
 291 }
 292
 293 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 294 {
 295     switch (miscReg) {
 296         // tick and stick are aliased to each other in niagra
 297       case MISCREG_TICK:
 298       case MISCREG_STICK:
 299       case MISCREG_PRIVTICK:
 300         // I'm not sure why legion ignores the lowest two bits, but we'll go
 301         // with it
 302         // change from curCycle() to instCount() until we're done with legion
 303         DPRINTFN("Instruction Count when STICK read: %#X\n",
 304                 tc->getCpuPtr()->instCount());
 305         return mbits(tc->getCpuPtr()->instCount() - (tick &
 306                     mask(63)),62,2) | mbits(tick,63,63) ;
 307       case MISCREG_FPRS:
 308         panic("FPU not implemented\n");
 309       case MISCREG_PCR:
 310       case MISCREG_PIC:
 311         panic("Performance Instrumentation not impl\n");
 312         /** Floating Point Status Register */
 313       case MISCREG_FSR:
 314         panic("Floating Point not implemented\n");
 315       case MISCREG_SOFTINT_CLR:
 316       case MISCREG_SOFTINT_SET:
 317         panic("Can read from softint clr/set\n");
 318       case MISCREG_SOFTINT:
 319       case MISCREG_TICK_CMPR:
 320       case MISCREG_STICK_CMPR:
 321       case MISCREG_HPSTATE:
 322       case MISCREG_HINTP:
 323       case MISCREG_HTSTATE:
 324       case MISCREG_HTBA:
 325       case MISCREG_HVER:
 326       case MISCREG_STRAND_STS_REG:
 327       case MISCREG_HSTICK_CMPR:
 328       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 329       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 330       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 331       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 332       case MISCREG_QUEUE_RES_ERROR_HEAD:
 333       case MISCREG_QUEUE_RES_ERROR_TAIL:
 334       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 335       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 336 #if FULL_SYSTEM
 337         return readFSRegWithEffect(miscReg, tc);
 338 #else
 339         panic("Accessing Fullsystem register is SE mode\n");
 340 #endif
 341
 342     }
 343     return readReg(miscReg);
 344 }
 345
 346 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 347 {
 348     switch (miscReg) {
 349       case MISCREG_Y:
 350         y = val;
 351         break;
 352       case MISCREG_CCR:
 353         ccr = val;
 354         break;
 355       case MISCREG_ASI:
 356         asi = val;
 357         break;
 358       case MISCREG_FPRS:
 359         fprs = val;
 360         break;
 361       case MISCREG_TICK:
 362         tick = val;
 363         break;
 364       case MISCREG_PCR:
 365         panic("PCR not implemented\n");
 366       case MISCREG_PIC:
 367         panic("PIC not implemented\n");
 368       case MISCREG_GSR:
 369         gsr = val;
 370         break;
 371       case MISCREG_SOFTINT:
 372         softint |= val;
 373         break;
 374       case MISCREG_TICK_CMPR:
 375         tick_cmpr = val;
 376         break;
 377       case MISCREG_STICK:
 378         stick = val;
 379         break;
 380       case MISCREG_STICK_CMPR:
 381         stick_cmpr = val;
 382         break;
 383
 384         /** Privilged Registers */
 385       case MISCREG_TPC:
 386         tpc[tl-1] = val;
 387         break;
 388       case MISCREG_TNPC:
 389         tnpc[tl-1] = val;
 390         break;
 391       case MISCREG_TSTATE:
 392         tstate[tl-1] = val;
 393         break;
 394       case MISCREG_TT:
 395         tt[tl-1] = val;
 396         break;
 397       case MISCREG_PRIVTICK:
 398         panic("Priviliged access to tick regesiters not implemented\n");
 399       case MISCREG_TBA:
 400         // clear lower 7 bits on writes.
 401         tba = val & ULL(~0x7FFF);
 402         break;
 403       case MISCREG_PSTATE:
 404         pstate = (val & PSTATE_MASK);
 405         break;
 406       case MISCREG_TL:
 407         tl = val;
 408         break;
 409       case MISCREG_PIL:
 410         pil = val;
 411         break;
 412       case MISCREG_CWP:
 413         cwp = val;
 414         break;
 415       case MISCREG_CANSAVE:
 416         cansave = val;
 417         break;
 418       case MISCREG_CANRESTORE:
 419         canrestore = val;
 420         break;
 421       case MISCREG_CLEANWIN:
 422         cleanwin = val;
 423         break;
 424       case MISCREG_OTHERWIN:
 425         otherwin = val;
 426         break;
 427       case MISCREG_WSTATE:
 428         wstate = val;
 429         break;
 430       case MISCREG_GL:
 431         gl = val;
 432         break;
 433
 434         /** Hyper privileged registers */
 435       case MISCREG_HPSTATE:
 436         hpstate = val;
 437         break;
 438       case MISCREG_HTSTATE:
 439         htstate[tl-1] = val;
 440         break;
 441       case MISCREG_HINTP:
 442         panic("HINTP not implemented\n");
 443       case MISCREG_HTBA:
 444         htba = val;
 445         break;
 446       case MISCREG_STRAND_STS_REG:
 447         strandStatusReg = val;
 448         break;
 449       case MISCREG_HSTICK_CMPR:
 450         hstick_cmpr = val;
 451         break;
 452
 453         /** Floating Point Status Register */
 454       case MISCREG_FSR:
 455         fsr = val;
 456         break;
 457
 458       case MISCREG_MMU_P_CONTEXT:
 459         priContext = val;
 460         break;
 461       case MISCREG_MMU_S_CONTEXT:
 462         secContext = val;
 463         break;
 464       case MISCREG_MMU_PART_ID:
 465         partId = val;
 466         break;
 467       case MISCREG_MMU_LSU_CTRL:
 468         lsuCtrlReg = val;
 469         break;
 470
 471       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 472         iTlbC0TsbPs0 = val;
 473         break;
 474       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 475         iTlbC0TsbPs1 = val;
 476         break;
 477       case MISCREG_MMU_ITLB_C0_CONFIG:
 478         iTlbC0Config = val;
 479         break;
 480       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 481         iTlbCXTsbPs0 = val;
 482         break;
 483       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 484         iTlbCXTsbPs1 = val;
 485         break;
 486       case MISCREG_MMU_ITLB_CX_CONFIG:
 487         iTlbCXConfig = val;
 488         break;
 489       case MISCREG_MMU_ITLB_SFSR:
 490         iTlbSfsr = val;
 491         break;
 492       case MISCREG_MMU_ITLB_TAG_ACCESS:
 493         iTlbTagAccess = val;
 494         break;
 495
 496       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 497         dTlbC0TsbPs0 = val;
 498         break;
 499       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 500         dTlbC0TsbPs1 = val;
 501         break;
 502       case MISCREG_MMU_DTLB_C0_CONFIG:
 503         dTlbC0Config = val;
 504         break;
 505       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 506         dTlbCXTsbPs0 = val;
 507         break;
 508       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 509         dTlbCXTsbPs1 = val;
 510         break;
 511       case MISCREG_MMU_DTLB_CX_CONFIG:
 512         dTlbCXConfig = val;
 513         break;
 514       case MISCREG_MMU_DTLB_SFSR:
 515         dTlbSfsr = val;
 516         break;
 517       case MISCREG_MMU_DTLB_SFAR:
 518         dTlbSfar = val;
 519         break;
 520       case MISCREG_MMU_DTLB_TAG_ACCESS:
 521         dTlbTagAccess = val;
 522         break;
 523
 524       case MISCREG_SCRATCHPAD_R0:
 525         scratchPad[0] = val;
 526         break;
 527       case MISCREG_SCRATCHPAD_R1:
 528         scratchPad[1] = val;
 529         break;
 530       case MISCREG_SCRATCHPAD_R2:
 531         scratchPad[2] = val;
 532         break;
 533       case MISCREG_SCRATCHPAD_R3:
 534         scratchPad[3] = val;
 535         break;
 536       case MISCREG_SCRATCHPAD_R4:
 537         scratchPad[4] = val;
 538         break;
 539       case MISCREG_SCRATCHPAD_R5:
 540         scratchPad[5] = val;
 541         break;
 542       case MISCREG_SCRATCHPAD_R6:
 543         scratchPad[6] = val;
 544         break;
 545       case MISCREG_SCRATCHPAD_R7:
 546         scratchPad[7] = val;
 547         break;
 548       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 549         cpu_mondo_head = val;
 550         break;
 551       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 552         cpu_mondo_tail = val;
 553         break;
 554       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 555         dev_mondo_head = val;
 556         break;
 557       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 558         dev_mondo_tail = val;
 559         break;
 560       case MISCREG_QUEUE_RES_ERROR_HEAD:
 561         res_error_head = val;
 562         break;
 563       case MISCREG_QUEUE_RES_ERROR_TAIL:
 564         res_error_tail = val;
 565         break;
 566       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 567         nres_error_head = val;
 568         break;
 569       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 570         nres_error_tail = val;
 571         break;
 572
 573       default:
 574         panic("Miscellaneous register %d not implemented\n", miscReg);
 575     }
 576 }
 577
 578 void MiscRegFile::setRegWithEffect(int miscReg,
 579         const MiscReg &val, ThreadContext * tc)
 580 {
 581     const uint64_t Bit64 = (1ULL << 63);
 582     switch (miscReg) {
 583       case MISCREG_STICK:
 584       case MISCREG_TICK:
 585         // change from curCycle() to instCount() until we're done with legion
 586         tick = tc->getCpuPtr()->instCount() - val  & ~Bit64;
 587         tick |= val & Bit64;
 588         break;
 589       case MISCREG_FPRS:
 590         //Configure the fpu based on the fprs
 591         break;
 592       case MISCREG_PCR:
 593         //Set up performance counting based on pcr value
 594         break;
 595       case MISCREG_PSTATE:
 596         pstate = val & PSTATE_MASK;
 597         return;
 598       case MISCREG_TL:
 599         tl = val;
 600         return;
 601       case MISCREG_CWP:
 602         tc->changeRegFileContext(CONTEXT_CWP, val);
 603         break;
 604       case MISCREG_GL:
 605         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 606         break;
 607       case MISCREG_PIL:
 608       case MISCREG_SOFTINT:
 609       case MISCREG_TICK_CMPR:
 610       case MISCREG_STICK_CMPR:
 611       case MISCREG_HPSTATE:
 612       case MISCREG_HINTP:
 613       case MISCREG_HTSTATE:
 614       case MISCREG_HTBA:
 615       case MISCREG_HVER:
 616       case MISCREG_STRAND_STS_REG:
 617       case MISCREG_HSTICK_CMPR:
 618       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 619       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 620       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 621       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 622       case MISCREG_QUEUE_RES_ERROR_HEAD:
 623       case MISCREG_QUEUE_RES_ERROR_TAIL:
 624       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 625       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 626 #if FULL_SYSTEM
 627         setFSRegWithEffect(miscReg, val, tc);
 628         return;
 629 #else
 630         panic("Accessing Fullsystem register is SE mode\n");
 631 #endif
 632     }
 633     setReg(miscReg, val);
 634 }
 635
 636 void MiscRegFile::serialize(std::ostream & os)
 637 {
 638     SERIALIZE_SCALAR(pstate);
 639     SERIALIZE_SCALAR(tba);
 640     SERIALIZE_SCALAR(y);
 641     SERIALIZE_SCALAR(pil);
 642     SERIALIZE_SCALAR(gl);
 643     SERIALIZE_SCALAR(cwp);
 644     SERIALIZE_ARRAY(tt, MaxTL);
 645     SERIALIZE_SCALAR(ccr);
 646     SERIALIZE_SCALAR(asi);
 647     SERIALIZE_SCALAR(tl);
 648     SERIALIZE_ARRAY(tpc, MaxTL);
 649     SERIALIZE_ARRAY(tnpc, MaxTL);
 650     SERIALIZE_ARRAY(tstate, MaxTL);
 651     SERIALIZE_SCALAR(tick);
 652     SERIALIZE_SCALAR(cansave);
 653     SERIALIZE_SCALAR(canrestore);
 654     SERIALIZE_SCALAR(otherwin);
 655     SERIALIZE_SCALAR(cleanwin);
 656     SERIALIZE_SCALAR(wstate);
 657     SERIALIZE_SCALAR(fsr);
 658     SERIALIZE_SCALAR(fprs);
 659     SERIALIZE_SCALAR(hpstate);
 660     SERIALIZE_ARRAY(htstate, MaxTL);
 661     SERIALIZE_SCALAR(htba);
 662     SERIALIZE_SCALAR(hstick_cmpr);
 663     SERIALIZE_SCALAR(strandStatusReg);
 664     SERIALIZE_SCALAR(priContext);
 665     SERIALIZE_SCALAR(secContext);
 666     SERIALIZE_SCALAR(partId);
 667     SERIALIZE_SCALAR(lsuCtrlReg);
 668     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 669     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 670     SERIALIZE_SCALAR(iTlbC0Config);
 671     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 672     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 673     SERIALIZE_SCALAR(iTlbCXConfig);
 674     SERIALIZE_SCALAR(iTlbSfsr);
 675     SERIALIZE_SCALAR(iTlbTagAccess);
 676     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 677     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 678     SERIALIZE_SCALAR(dTlbC0Config);
 679     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 680     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 681     SERIALIZE_SCALAR(dTlbSfsr);
 682     SERIALIZE_SCALAR(dTlbSfar);
 683     SERIALIZE_SCALAR(dTlbTagAccess);
 684     SERIALIZE_ARRAY(scratchPad,8);
 685     SERIALIZE_SCALAR(cpu_mondo_head);
 686     SERIALIZE_SCALAR(cpu_mondo_tail);
 687     SERIALIZE_SCALAR(dev_mondo_head);
 688     SERIALIZE_SCALAR(dev_mondo_tail);
 689     SERIALIZE_SCALAR(res_error_head);
 690     SERIALIZE_SCALAR(res_error_tail);
 691     SERIALIZE_SCALAR(nres_error_head);
 692     SERIALIZE_SCALAR(nres_error_tail);
 693 }
 694
 695 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 696 {
 697     UNSERIALIZE_SCALAR(pstate);
 698     UNSERIALIZE_SCALAR(tba);
 699     UNSERIALIZE_SCALAR(y);
 700     UNSERIALIZE_SCALAR(pil);
 701     UNSERIALIZE_SCALAR(gl);
 702     UNSERIALIZE_SCALAR(cwp);
 703     UNSERIALIZE_ARRAY(tt, MaxTL);
 704     UNSERIALIZE_SCALAR(ccr);
 705     UNSERIALIZE_SCALAR(asi);
 706     UNSERIALIZE_SCALAR(tl);
 707     UNSERIALIZE_ARRAY(tpc, MaxTL);
 708     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 709     UNSERIALIZE_ARRAY(tstate, MaxTL);
 710     UNSERIALIZE_SCALAR(tick);
 711     UNSERIALIZE_SCALAR(cansave);
 712     UNSERIALIZE_SCALAR(canrestore);
 713     UNSERIALIZE_SCALAR(otherwin);
 714     UNSERIALIZE_SCALAR(cleanwin);
 715     UNSERIALIZE_SCALAR(wstate);
 716     UNSERIALIZE_SCALAR(fsr);
 717     UNSERIALIZE_SCALAR(fprs);
 718     UNSERIALIZE_SCALAR(hpstate);
 719     UNSERIALIZE_ARRAY(htstate, MaxTL);
 720     UNSERIALIZE_SCALAR(htba);
 721     UNSERIALIZE_SCALAR(hstick_cmpr);
 722     UNSERIALIZE_SCALAR(strandStatusReg);
 723     UNSERIALIZE_SCALAR(priContext);
 724     UNSERIALIZE_SCALAR(secContext);
 725     UNSERIALIZE_SCALAR(partId);
 726     UNSERIALIZE_SCALAR(lsuCtrlReg);
 727     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 728     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 729     UNSERIALIZE_SCALAR(iTlbC0Config);
 730     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 731     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 732     UNSERIALIZE_SCALAR(iTlbCXConfig);
 733     UNSERIALIZE_SCALAR(iTlbSfsr);
 734     UNSERIALIZE_SCALAR(iTlbTagAccess);
 735     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 736     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 737     UNSERIALIZE_SCALAR(dTlbC0Config);
 738     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 739     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 740     UNSERIALIZE_SCALAR(dTlbSfsr);
 741     UNSERIALIZE_SCALAR(dTlbSfar);
 742     UNSERIALIZE_SCALAR(dTlbTagAccess);
 743     UNSERIALIZE_ARRAY(scratchPad,8);
 744     UNSERIALIZE_SCALAR(cpu_mondo_head);
 745     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 746     UNSERIALIZE_SCALAR(dev_mondo_head);
 747     UNSERIALIZE_SCALAR(dev_mondo_tail);
 748     UNSERIALIZE_SCALAR(res_error_head);
 749     UNSERIALIZE_SCALAR(res_error_tail);
 750     UNSERIALIZE_SCALAR(nres_error_head);
 751     UNSERIALIZE_SCALAR(nres_error_tail);}