src/arch/sparc/miscregfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/asi.hh"
  33 #include "arch/sparc/miscregfile.hh"
  34 #include "base/bitfield.hh"
  35 #include "base/trace.hh"
  36 #include "config/full_system.hh"
  37 #include "cpu/base.hh"
  38 #include "cpu/thread_context.hh"
  39
  40 using namespace SparcISA;
  41 using namespace std;
  42
  43 class Checkpoint;
  44
  45 //These functions map register indices to names
  46 string SparcISA::getMiscRegName(RegIndex index)
  47 {
  48     static::string miscRegName[NumMiscRegs] =
  49        {"y", "ccr", "asi", "tick", "fprs", "pcr", "pic",
  50         "gsr", "softint_set", "softint_clr", "softint", "tick_cmpr",
  51         "stick", "stick_cmpr",
  52         "tpc", "tnpc", "tstate", "tt", "privtick", "tba", "pstate", "tl",
  53         "pil", "cwp", "cansave", "canrestore", "cleanwin", "otherwin",
  54         "wstate", "gl",
  55         "hpstate", "htstate", "hintp", "htba", "hver", "strand_sts_reg",
  56         "hstick_cmpr",
  57         "fsr"};
  58     return miscRegName[index];
  59 }
  60
  61 enum RegMask
  62 {
  63         PSTATE_MASK = (((1 << 4) - 1) << 1) | (((1 << 4) - 1) << 6) | (1 << 12)
  64 };
  65
  66 void MiscRegFile::clear()
  67 {
  68     y = 0;
  69     ccr = 0;
  70     asi = 0;
  71     tick = ULL(1) << 63;
  72     fprs = 0;
  73     gsr = 0;
  74     softint = 0;
  75     tick_cmpr = 0;
  76     stick = 0;
  77     stick_cmpr = 0;
  78     memset(tpc, 0, sizeof(tpc));
  79     memset(tnpc, 0, sizeof(tnpc));
  80     memset(tstate, 0, sizeof(tstate));
  81     memset(tt, 0, sizeof(tt));
  82     pstate = 0;
  83     tl = 0;
  84     pil = 0;
  85     cwp = 0;
  86     cansave = 0;
  87     canrestore = 0;
  88     cleanwin = 0;
  89     otherwin = 0;
  90     wstate = 0;
  91     gl = 0;
  92     //In a T1, bit 11 is apparently always 1
  93     hpstate = (1 << 11);
  94     memset(htstate, 0, sizeof(htstate));
  95     hintp = 0;
  96     htba = 0;
  97     hstick_cmpr = 0;
  98     //This is set this way in Legion for some reason
  99     strandStatusReg = 0x50000;
 100     fsr = 0;
 101
 102     priContext = 0;
 103     secContext = 0;
 104     partId = 0;
 105     lsuCtrlReg = 0;
 106
 107     iTlbC0TsbPs0 = 0;
 108     iTlbC0TsbPs1 = 0;
 109     iTlbC0Config = 0;
 110     iTlbCXTsbPs0 = 0;
 111     iTlbCXTsbPs1 = 0;
 112     iTlbCXConfig = 0;
 113     iTlbSfsr = 0;
 114     iTlbTagAccess = 0;
 115
 116     dTlbC0TsbPs0 = 0;
 117     dTlbC0TsbPs1 = 0;
 118     dTlbC0Config = 0;
 119     dTlbCXTsbPs0 = 0;
 120     dTlbCXTsbPs1 = 0;
 121     dTlbCXConfig = 0;
 122     dTlbSfsr = 0;
 123     dTlbSfar = 0;
 124     dTlbTagAccess = 0;
 125
 126     memset(scratchPad, 0, sizeof(scratchPad));
 127 }
 128
 129 MiscReg MiscRegFile::readReg(int miscReg)
 130 {
 131     switch (miscReg) {
 132       case MISCREG_TLB_DATA:
 133         /* Package up all the data for the tlb:
 134          * 6666555555555544444444443333333333222222222211111111110000000000
 135          * 3210987654321098765432109876543210987654321098765432109876543210
 136          *   secContext   | priContext    |             |tl|partid|  |||||^hpriv
 137          *                                                           ||||^red
 138          *                                                           |||^priv
 139          *                                                           ||^am
 140          *                                                           |^lsuim
 141          *                                                           ^lsudm
 142          */
 143         return bits((uint64_t)hpstate,2,2) |
 144                bits((uint64_t)hpstate,5,5) << 1 |
 145                bits((uint64_t)pstate,3,2) << 2 |
 146                bits((uint64_t)lsuCtrlReg,3,2) << 4 |
 147                bits((uint64_t)partId,7,0) << 8 |
 148                bits((uint64_t)tl,2,0) << 16 |
 149                (uint64_t)priContext << 32 |
 150                (uint64_t)secContext << 48;
 151
 152       case MISCREG_Y:
 153         return y;
 154       case MISCREG_CCR:
 155         return ccr;
 156       case MISCREG_ASI:
 157         return asi;
 158       case MISCREG_FPRS:
 159         return fprs;
 160       case MISCREG_TICK:
 161         return tick;
 162       case MISCREG_PCR:
 163         panic("PCR not implemented\n");
 164       case MISCREG_PIC:
 165         panic("PIC not implemented\n");
 166       case MISCREG_GSR:
 167         return gsr;
 168       case MISCREG_SOFTINT:
 169         return softint;
 170       case MISCREG_TICK_CMPR:
 171         return tick_cmpr;
 172       case MISCREG_STICK:
 173         return stick;
 174       case MISCREG_STICK_CMPR:
 175         return stick_cmpr;
 176
 177         /** Privilged Registers */
 178       case MISCREG_TPC:
 179         return tpc[tl-1];
 180       case MISCREG_TNPC:
 181         return tnpc[tl-1];
 182       case MISCREG_TSTATE:
 183         return tstate[tl-1];
 184       case MISCREG_TT:
 185         return tt[tl-1];
 186       case MISCREG_PRIVTICK:
 187         panic("Priviliged access to tick registers not implemented\n");
 188       case MISCREG_TBA:
 189         return tba;
 190       case MISCREG_PSTATE:
 191         return pstate;
 192       case MISCREG_TL:
 193         return tl;
 194       case MISCREG_PIL:
 195         return pil;
 196       case MISCREG_CWP:
 197         return cwp;
 198       case MISCREG_CANSAVE:
 199         return cansave;
 200       case MISCREG_CANRESTORE:
 201         return canrestore;
 202       case MISCREG_CLEANWIN:
 203         return cleanwin;
 204       case MISCREG_OTHERWIN:
 205         return otherwin;
 206       case MISCREG_WSTATE:
 207         return wstate;
 208       case MISCREG_GL:
 209         return gl;
 210
 211         /** Hyper privileged registers */
 212       case MISCREG_HPSTATE:
 213         return hpstate;
 214       case MISCREG_HTSTATE:
 215         return htstate[tl-1];
 216       case MISCREG_HINTP:
 217         return hintp;
 218       case MISCREG_HTBA:
 219         return htba;
 220       case MISCREG_HVER:
 221         return NWindows | MaxTL << 8 | MaxGL << 16;
 222       case MISCREG_STRAND_STS_REG:
 223         return strandStatusReg;
 224       case MISCREG_HSTICK_CMPR:
 225         return hstick_cmpr;
 226
 227         /** Floating Point Status Register */
 228       case MISCREG_FSR:
 229         return fsr;
 230
 231       case MISCREG_MMU_P_CONTEXT:
 232         return priContext;
 233       case MISCREG_MMU_S_CONTEXT:
 234         return secContext;
 235       case MISCREG_MMU_PART_ID:
 236         return partId;
 237       case MISCREG_MMU_LSU_CTRL:
 238         return lsuCtrlReg;
 239
 240       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 241         return iTlbC0TsbPs0;
 242       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 243         return iTlbC0TsbPs1;
 244       case MISCREG_MMU_ITLB_C0_CONFIG:
 245         return iTlbC0Config;
 246       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 247         return iTlbCXTsbPs0;
 248       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 249         return iTlbCXTsbPs1;
 250       case MISCREG_MMU_ITLB_CX_CONFIG:
 251         return iTlbCXConfig;
 252       case MISCREG_MMU_ITLB_SFSR:
 253         return iTlbSfsr;
 254       case MISCREG_MMU_ITLB_TAG_ACCESS:
 255         return iTlbTagAccess;
 256
 257       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 258         return dTlbC0TsbPs0;
 259       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 260         return dTlbC0TsbPs1;
 261       case MISCREG_MMU_DTLB_C0_CONFIG:
 262         return dTlbC0Config;
 263       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 264         return dTlbCXTsbPs0;
 265       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 266         return dTlbCXTsbPs1;
 267       case MISCREG_MMU_DTLB_CX_CONFIG:
 268         return dTlbCXConfig;
 269       case MISCREG_MMU_DTLB_SFSR:
 270         return dTlbSfsr;
 271       case MISCREG_MMU_DTLB_SFAR:
 272         return dTlbSfar;
 273       case MISCREG_MMU_DTLB_TAG_ACCESS:
 274         return dTlbTagAccess;
 275
 276       case MISCREG_SCRATCHPAD_R0:
 277         return scratchPad[0];
 278       case MISCREG_SCRATCHPAD_R1:
 279         return scratchPad[1];
 280       case MISCREG_SCRATCHPAD_R2:
 281         return scratchPad[2];
 282       case MISCREG_SCRATCHPAD_R3:
 283         return scratchPad[3];
 284       case MISCREG_SCRATCHPAD_R4:
 285         return scratchPad[4];
 286       case MISCREG_SCRATCHPAD_R5:
 287         return scratchPad[5];
 288       case MISCREG_SCRATCHPAD_R6:
 289         return scratchPad[6];
 290       case MISCREG_SCRATCHPAD_R7:
 291         return scratchPad[7];
 292       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 293         return cpu_mondo_head;
 294       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 295         return cpu_mondo_tail;
 296       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 297         return dev_mondo_head;
 298       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 299         return dev_mondo_tail;
 300       case MISCREG_QUEUE_RES_ERROR_HEAD:
 301         return res_error_head;
 302       case MISCREG_QUEUE_RES_ERROR_TAIL:
 303         return res_error_tail;
 304       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 305         return nres_error_head;
 306       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 307         return nres_error_tail;
 308       default:
 309         panic("Miscellaneous register %d not implemented\n", miscReg);
 310     }
 311 }
 312
 313 MiscReg MiscRegFile::readRegWithEffect(int miscReg, ThreadContext * tc)
 314 {
 315     switch (miscReg) {
 316         // tick and stick are aliased to each other in niagra
 317         // well store the tick data in stick and the interrupt bit in tick
 318       case MISCREG_STICK:
 319       case MISCREG_TICK:
 320       case MISCREG_PRIVTICK:
 321         // I'm not sure why legion ignores the lowest two bits, but we'll go
 322         // with it
 323         // change from curCycle() to instCount() until we're done with legion
 324         DPRINTF(Timer, "Instruction Count when TICK read: %#X stick=%#X\n",
 325                 tc->getCpuPtr()->instCount(), stick);
 326         return mbits(tc->getCpuPtr()->instCount() + (int64_t)stick,62,2) |
 327                mbits(tick,63,63);
 328       case MISCREG_FPRS:
 329         // in legion if fp is enabled du and dl are set
 330         return fprs | 0x3;
 331       case MISCREG_PCR:
 332       case MISCREG_PIC:
 333         panic("Performance Instrumentation not impl\n");
 334         /** Floating Point Status Register */
 335       case MISCREG_FSR:
 336         warn("Reading FSR Floating Point not implemented\n");
 337         break;
 338       case MISCREG_SOFTINT_CLR:
 339       case MISCREG_SOFTINT_SET:
 340         panic("Can read from softint clr/set\n");
 341       case MISCREG_SOFTINT:
 342       case MISCREG_TICK_CMPR:
 343       case MISCREG_STICK_CMPR:
 344       case MISCREG_HINTP:
 345       case MISCREG_HTSTATE:
 346       case MISCREG_HTBA:
 347       case MISCREG_HVER:
 348       case MISCREG_STRAND_STS_REG:
 349       case MISCREG_HSTICK_CMPR:
 350       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 351       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 352       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 353       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 354       case MISCREG_QUEUE_RES_ERROR_HEAD:
 355       case MISCREG_QUEUE_RES_ERROR_TAIL:
 356       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 357       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 358 #if FULL_SYSTEM
 359       case MISCREG_HPSTATE:
 360         return readFSRegWithEffect(miscReg, tc);
 361 #else
 362       case MISCREG_HPSTATE:
 363         //HPSTATE is special because because sometimes in privilege checks for instructions
 364         //it will read HPSTATE to make sure the priv. level is ok
 365         //So, we'll just have to tell it it isn't, instead of panicing.
 366         return 0;
 367
 368       panic("Accessing Fullsystem register %s in SE mode\n",getMiscRegName(miscReg));
 369 #endif
 370
 371     }
 372     return readReg(miscReg);
 373 }
 374
 375 void MiscRegFile::setReg(int miscReg, const MiscReg &val)
 376 {
 377     switch (miscReg) {
 378       case MISCREG_Y:
 379         y = val;
 380         break;
 381       case MISCREG_CCR:
 382         ccr = val;
 383         break;
 384       case MISCREG_ASI:
 385         asi = val;
 386         break;
 387       case MISCREG_FPRS:
 388         fprs = val;
 389         break;
 390       case MISCREG_TICK:
 391         tick = val;
 392         break;
 393       case MISCREG_PCR:
 394         panic("PCR not implemented\n");
 395       case MISCREG_PIC:
 396         panic("PIC not implemented\n");
 397       case MISCREG_GSR:
 398         gsr = val;
 399         break;
 400       case MISCREG_SOFTINT:
 401         softint = val;
 402         break;
 403       case MISCREG_TICK_CMPR:
 404         tick_cmpr = val;
 405         break;
 406       case MISCREG_STICK:
 407         stick = val;
 408         break;
 409       case MISCREG_STICK_CMPR:
 410         stick_cmpr = val;
 411         break;
 412
 413         /** Privilged Registers */
 414       case MISCREG_TPC:
 415         tpc[tl-1] = val;
 416         break;
 417       case MISCREG_TNPC:
 418         tnpc[tl-1] = val;
 419         break;
 420       case MISCREG_TSTATE:
 421         tstate[tl-1] = val;
 422         break;
 423       case MISCREG_TT:
 424         tt[tl-1] = val;
 425         break;
 426       case MISCREG_PRIVTICK:
 427         panic("Priviliged access to tick regesiters not implemented\n");
 428       case MISCREG_TBA:
 429         // clear lower 7 bits on writes.
 430         tba = val & ULL(~0x7FFF);
 431         break;
 432       case MISCREG_PSTATE:
 433         pstate = (val & PSTATE_MASK);
 434         break;
 435       case MISCREG_TL:
 436         tl = val;
 437         break;
 438       case MISCREG_PIL:
 439         pil = val;
 440         break;
 441       case MISCREG_CWP:
 442         cwp = val;
 443         break;
 444       case MISCREG_CANSAVE:
 445         cansave = val;
 446         break;
 447       case MISCREG_CANRESTORE:
 448         canrestore = val;
 449         break;
 450       case MISCREG_CLEANWIN:
 451         cleanwin = val;
 452         break;
 453       case MISCREG_OTHERWIN:
 454         otherwin = val;
 455         break;
 456       case MISCREG_WSTATE:
 457         wstate = val;
 458         break;
 459       case MISCREG_GL:
 460         gl = val;
 461         break;
 462
 463         /** Hyper privileged registers */
 464       case MISCREG_HPSTATE:
 465         hpstate = val;
 466         break;
 467       case MISCREG_HTSTATE:
 468         htstate[tl-1] = val;
 469         break;
 470       case MISCREG_HINTP:
 471         hintp = val;
 472       case MISCREG_HTBA:
 473         htba = val;
 474         break;
 475       case MISCREG_STRAND_STS_REG:
 476         strandStatusReg = val;
 477         break;
 478       case MISCREG_HSTICK_CMPR:
 479         hstick_cmpr = val;
 480         break;
 481
 482         /** Floating Point Status Register */
 483       case MISCREG_FSR:
 484         fsr = val;
 485         break;
 486
 487       case MISCREG_MMU_P_CONTEXT:
 488         priContext = val;
 489         break;
 490       case MISCREG_MMU_S_CONTEXT:
 491         secContext = val;
 492         break;
 493       case MISCREG_MMU_PART_ID:
 494         partId = val;
 495         break;
 496       case MISCREG_MMU_LSU_CTRL:
 497         lsuCtrlReg = val;
 498         break;
 499
 500       case MISCREG_MMU_ITLB_C0_TSB_PS0:
 501         iTlbC0TsbPs0 = val;
 502         break;
 503       case MISCREG_MMU_ITLB_C0_TSB_PS1:
 504         iTlbC0TsbPs1 = val;
 505         break;
 506       case MISCREG_MMU_ITLB_C0_CONFIG:
 507         iTlbC0Config = val;
 508         break;
 509       case MISCREG_MMU_ITLB_CX_TSB_PS0:
 510         iTlbCXTsbPs0 = val;
 511         break;
 512       case MISCREG_MMU_ITLB_CX_TSB_PS1:
 513         iTlbCXTsbPs1 = val;
 514         break;
 515       case MISCREG_MMU_ITLB_CX_CONFIG:
 516         iTlbCXConfig = val;
 517         break;
 518       case MISCREG_MMU_ITLB_SFSR:
 519         iTlbSfsr = val;
 520         break;
 521       case MISCREG_MMU_ITLB_TAG_ACCESS:
 522         iTlbTagAccess = val;
 523         break;
 524
 525       case MISCREG_MMU_DTLB_C0_TSB_PS0:
 526         dTlbC0TsbPs0 = val;
 527         break;
 528       case MISCREG_MMU_DTLB_C0_TSB_PS1:
 529         dTlbC0TsbPs1 = val;
 530         break;
 531       case MISCREG_MMU_DTLB_C0_CONFIG:
 532         dTlbC0Config = val;
 533         break;
 534       case MISCREG_MMU_DTLB_CX_TSB_PS0:
 535         dTlbCXTsbPs0 = val;
 536         break;
 537       case MISCREG_MMU_DTLB_CX_TSB_PS1:
 538         dTlbCXTsbPs1 = val;
 539         break;
 540       case MISCREG_MMU_DTLB_CX_CONFIG:
 541         dTlbCXConfig = val;
 542         break;
 543       case MISCREG_MMU_DTLB_SFSR:
 544         dTlbSfsr = val;
 545         break;
 546       case MISCREG_MMU_DTLB_SFAR:
 547         dTlbSfar = val;
 548         break;
 549       case MISCREG_MMU_DTLB_TAG_ACCESS:
 550         dTlbTagAccess = val;
 551         break;
 552
 553       case MISCREG_SCRATCHPAD_R0:
 554         scratchPad[0] = val;
 555         break;
 556       case MISCREG_SCRATCHPAD_R1:
 557         scratchPad[1] = val;
 558         break;
 559       case MISCREG_SCRATCHPAD_R2:
 560         scratchPad[2] = val;
 561         break;
 562       case MISCREG_SCRATCHPAD_R3:
 563         scratchPad[3] = val;
 564         break;
 565       case MISCREG_SCRATCHPAD_R4:
 566         scratchPad[4] = val;
 567         break;
 568       case MISCREG_SCRATCHPAD_R5:
 569         scratchPad[5] = val;
 570         break;
 571       case MISCREG_SCRATCHPAD_R6:
 572         scratchPad[6] = val;
 573         break;
 574       case MISCREG_SCRATCHPAD_R7:
 575         scratchPad[7] = val;
 576         break;
 577       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 578         cpu_mondo_head = val;
 579         break;
 580       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 581         cpu_mondo_tail = val;
 582         break;
 583       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 584         dev_mondo_head = val;
 585         break;
 586       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 587         dev_mondo_tail = val;
 588         break;
 589       case MISCREG_QUEUE_RES_ERROR_HEAD:
 590         res_error_head = val;
 591         break;
 592       case MISCREG_QUEUE_RES_ERROR_TAIL:
 593         res_error_tail = val;
 594         break;
 595       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 596         nres_error_head = val;
 597         break;
 598       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 599         nres_error_tail = val;
 600         break;
 601
 602       default:
 603         panic("Miscellaneous register %d not implemented\n", miscReg);
 604     }
 605 }
 606
 607 void MiscRegFile::setRegWithEffect(int miscReg,
 608         const MiscReg &val, ThreadContext * tc)
 609 {
 610     MiscReg new_val = val;
 611
 612     switch (miscReg) {
 613       case MISCREG_STICK:
 614       case MISCREG_TICK:
 615         // stick and tick are same thing on niagra
 616         // use stick for offset and tick for holding intrrupt bit
 617         stick = mbits(val,62,0) - tc->getCpuPtr()->instCount();
 618         tick = mbits(val,63,63);
 619         DPRINTF(Timer, "Writing TICK=%#X\n", val);
 620         break;
 621       case MISCREG_FPRS:
 622         //Configure the fpu based on the fprs
 623         break;
 624       case MISCREG_PCR:
 625         //Set up performance counting based on pcr value
 626         break;
 627       case MISCREG_PSTATE:
 628         pstate = val & PSTATE_MASK;
 629         return;
 630       case MISCREG_TL:
 631         tl = val;
 632         return;
 633       case MISCREG_CWP:
 634         new_val = val > NWindows ? NWindows - 1 : val;
 635         tc->changeRegFileContext(CONTEXT_CWP, new_val);
 636         break;
 637       case MISCREG_GL:
 638         tc->changeRegFileContext(CONTEXT_GLOBALS, val);
 639         break;
 640       case MISCREG_PIL:
 641       case MISCREG_SOFTINT:
 642       case MISCREG_SOFTINT_SET:
 643       case MISCREG_SOFTINT_CLR:
 644       case MISCREG_TICK_CMPR:
 645       case MISCREG_STICK_CMPR:
 646       case MISCREG_HINTP:
 647       case MISCREG_HTSTATE:
 648       case MISCREG_HTBA:
 649       case MISCREG_HVER:
 650       case MISCREG_STRAND_STS_REG:
 651       case MISCREG_HSTICK_CMPR:
 652       case MISCREG_QUEUE_CPU_MONDO_HEAD:
 653       case MISCREG_QUEUE_CPU_MONDO_TAIL:
 654       case MISCREG_QUEUE_DEV_MONDO_HEAD:
 655       case MISCREG_QUEUE_DEV_MONDO_TAIL:
 656       case MISCREG_QUEUE_RES_ERROR_HEAD:
 657       case MISCREG_QUEUE_RES_ERROR_TAIL:
 658       case MISCREG_QUEUE_NRES_ERROR_HEAD:
 659       case MISCREG_QUEUE_NRES_ERROR_TAIL:
 660 #if FULL_SYSTEM
 661       case MISCREG_HPSTATE:
 662         setFSRegWithEffect(miscReg, val, tc);
 663         return;
 664 #else
 665       case MISCREG_HPSTATE:
 666         //HPSTATE is special because normal trap processing saves HPSTATE when
 667         //it goes into a trap, and restores it when it returns.
 668         return;
 669       panic("Accessing Fullsystem register %s to %#x in SE mode\n", getMiscRegName(miscReg), val);
 670 #endif
 671     }
 672     setReg(miscReg, new_val);
 673 }
 674
 675 void MiscRegFile::serialize(std::ostream & os)
 676 {
 677     SERIALIZE_SCALAR(pstate);
 678     SERIALIZE_SCALAR(tba);
 679     SERIALIZE_SCALAR(y);
 680     SERIALIZE_SCALAR(pil);
 681     SERIALIZE_SCALAR(gl);
 682     SERIALIZE_SCALAR(cwp);
 683     SERIALIZE_ARRAY(tt, MaxTL);
 684     SERIALIZE_SCALAR(ccr);
 685     SERIALIZE_SCALAR(asi);
 686     SERIALIZE_SCALAR(tl);
 687     SERIALIZE_ARRAY(tpc, MaxTL);
 688     SERIALIZE_ARRAY(tnpc, MaxTL);
 689     SERIALIZE_ARRAY(tstate, MaxTL);
 690     SERIALIZE_SCALAR(tick);
 691     SERIALIZE_SCALAR(cansave);
 692     SERIALIZE_SCALAR(canrestore);
 693     SERIALIZE_SCALAR(otherwin);
 694     SERIALIZE_SCALAR(cleanwin);
 695     SERIALIZE_SCALAR(wstate);
 696     SERIALIZE_SCALAR(fsr);
 697     SERIALIZE_SCALAR(fprs);
 698     SERIALIZE_SCALAR(hpstate);
 699     SERIALIZE_ARRAY(htstate, MaxTL);
 700     SERIALIZE_SCALAR(htba);
 701     SERIALIZE_SCALAR(hstick_cmpr);
 702     SERIALIZE_SCALAR(strandStatusReg);
 703     SERIALIZE_SCALAR(priContext);
 704     SERIALIZE_SCALAR(secContext);
 705     SERIALIZE_SCALAR(partId);
 706     SERIALIZE_SCALAR(lsuCtrlReg);
 707     SERIALIZE_SCALAR(iTlbC0TsbPs0);
 708     SERIALIZE_SCALAR(iTlbC0TsbPs1);
 709     SERIALIZE_SCALAR(iTlbC0Config);
 710     SERIALIZE_SCALAR(iTlbCXTsbPs0);
 711     SERIALIZE_SCALAR(iTlbCXTsbPs1);
 712     SERIALIZE_SCALAR(iTlbCXConfig);
 713     SERIALIZE_SCALAR(iTlbSfsr);
 714     SERIALIZE_SCALAR(iTlbTagAccess);
 715     SERIALIZE_SCALAR(dTlbC0TsbPs0);
 716     SERIALIZE_SCALAR(dTlbC0TsbPs1);
 717     SERIALIZE_SCALAR(dTlbC0Config);
 718     SERIALIZE_SCALAR(dTlbCXTsbPs0);
 719     SERIALIZE_SCALAR(dTlbCXTsbPs1);
 720     SERIALIZE_SCALAR(dTlbSfsr);
 721     SERIALIZE_SCALAR(dTlbSfar);
 722     SERIALIZE_SCALAR(dTlbTagAccess);
 723     SERIALIZE_ARRAY(scratchPad,8);
 724     SERIALIZE_SCALAR(cpu_mondo_head);
 725     SERIALIZE_SCALAR(cpu_mondo_tail);
 726     SERIALIZE_SCALAR(dev_mondo_head);
 727     SERIALIZE_SCALAR(dev_mondo_tail);
 728     SERIALIZE_SCALAR(res_error_head);
 729     SERIALIZE_SCALAR(res_error_tail);
 730     SERIALIZE_SCALAR(nres_error_head);
 731     SERIALIZE_SCALAR(nres_error_tail);
 732 }
 733
 734 void MiscRegFile::unserialize(Checkpoint * cp, const std::string & section)
 735 {
 736     UNSERIALIZE_SCALAR(pstate);
 737     UNSERIALIZE_SCALAR(tba);
 738     UNSERIALIZE_SCALAR(y);
 739     UNSERIALIZE_SCALAR(pil);
 740     UNSERIALIZE_SCALAR(gl);
 741     UNSERIALIZE_SCALAR(cwp);
 742     UNSERIALIZE_ARRAY(tt, MaxTL);
 743     UNSERIALIZE_SCALAR(ccr);
 744     UNSERIALIZE_SCALAR(asi);
 745     UNSERIALIZE_SCALAR(tl);
 746     UNSERIALIZE_ARRAY(tpc, MaxTL);
 747     UNSERIALIZE_ARRAY(tnpc, MaxTL);
 748     UNSERIALIZE_ARRAY(tstate, MaxTL);
 749     UNSERIALIZE_SCALAR(tick);
 750     UNSERIALIZE_SCALAR(cansave);
 751     UNSERIALIZE_SCALAR(canrestore);
 752     UNSERIALIZE_SCALAR(otherwin);
 753     UNSERIALIZE_SCALAR(cleanwin);
 754     UNSERIALIZE_SCALAR(wstate);
 755     UNSERIALIZE_SCALAR(fsr);
 756     UNSERIALIZE_SCALAR(fprs);
 757     UNSERIALIZE_SCALAR(hpstate);
 758     UNSERIALIZE_ARRAY(htstate, MaxTL);
 759     UNSERIALIZE_SCALAR(htba);
 760     UNSERIALIZE_SCALAR(hstick_cmpr);
 761     UNSERIALIZE_SCALAR(strandStatusReg);
 762     UNSERIALIZE_SCALAR(priContext);
 763     UNSERIALIZE_SCALAR(secContext);
 764     UNSERIALIZE_SCALAR(partId);
 765     UNSERIALIZE_SCALAR(lsuCtrlReg);
 766     UNSERIALIZE_SCALAR(iTlbC0TsbPs0);
 767     UNSERIALIZE_SCALAR(iTlbC0TsbPs1);
 768     UNSERIALIZE_SCALAR(iTlbC0Config);
 769     UNSERIALIZE_SCALAR(iTlbCXTsbPs0);
 770     UNSERIALIZE_SCALAR(iTlbCXTsbPs1);
 771     UNSERIALIZE_SCALAR(iTlbCXConfig);
 772     UNSERIALIZE_SCALAR(iTlbSfsr);
 773     UNSERIALIZE_SCALAR(iTlbTagAccess);
 774     UNSERIALIZE_SCALAR(dTlbC0TsbPs0);
 775     UNSERIALIZE_SCALAR(dTlbC0TsbPs1);
 776     UNSERIALIZE_SCALAR(dTlbC0Config);
 777     UNSERIALIZE_SCALAR(dTlbCXTsbPs0);
 778     UNSERIALIZE_SCALAR(dTlbCXTsbPs1);
 779     UNSERIALIZE_SCALAR(dTlbSfsr);
 780     UNSERIALIZE_SCALAR(dTlbSfar);
 781     UNSERIALIZE_SCALAR(dTlbTagAccess);
 782     UNSERIALIZE_ARRAY(scratchPad,8);
 783     UNSERIALIZE_SCALAR(cpu_mondo_head);
 784     UNSERIALIZE_SCALAR(cpu_mondo_tail);
 785     UNSERIALIZE_SCALAR(dev_mondo_head);
 786     UNSERIALIZE_SCALAR(dev_mondo_tail);
 787     UNSERIALIZE_SCALAR(res_error_head);
 788     UNSERIALIZE_SCALAR(res_error_tail);
 789     UNSERIALIZE_SCALAR(nres_error_head);
 790     UNSERIALIZE_SCALAR(nres_error_tail);}