src/arch/sparc/miscregfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
  33 #define __ARCH_SPARC_MISCREGFILE_HH__
  34
  35 #include "arch/sparc/faults.hh"
  36 #include "arch/sparc/isa_traits.hh"
  37 #include "arch/sparc/types.hh"
  38 #include "cpu/cpuevent.hh"
  39
  40 #include <string>
  41
  42 class Checkpoint;
  43
  44 namespace SparcISA
  45 {
  46     enum MiscRegIndex
  47     {
  48         /** Ancillary State Registers */
  49 //        MISCREG_Y,
  50 //        MISCREG_CCR,
  51         MISCREG_ASI,
  52         MISCREG_TICK,
  53         MISCREG_FPRS,
  54         MISCREG_PCR,
  55         MISCREG_PIC,
  56         MISCREG_GSR,
  57         MISCREG_SOFTINT_SET,
  58         MISCREG_SOFTINT_CLR,
  59         MISCREG_SOFTINT, /* 10 */
  60         MISCREG_TICK_CMPR,
  61         MISCREG_STICK,
  62         MISCREG_STICK_CMPR,
  63
  64         /** Privilged Registers */
  65         MISCREG_TPC,
  66         MISCREG_TNPC,
  67         MISCREG_TSTATE,
  68         MISCREG_TT,
  69         MISCREG_PRIVTICK,
  70         MISCREG_TBA,
  71         MISCREG_PSTATE, /* 20 */
  72         MISCREG_TL,
  73         MISCREG_PIL,
  74         MISCREG_CWP,
  75 //        MISCREG_CANSAVE,
  76 //        MISCREG_CANRESTORE,
  77 //        MISCREG_CLEANWIN,
  78 //        MISCREG_OTHERWIN,
  79 //        MISCREG_WSTATE,
  80         MISCREG_GL,
  81
  82         /** Hyper privileged registers */
  83         MISCREG_HPSTATE, /* 30 */
  84         MISCREG_HTSTATE,
  85         MISCREG_HINTP,
  86         MISCREG_HTBA,
  87         MISCREG_HVER,
  88         MISCREG_STRAND_STS_REG,
  89         MISCREG_HSTICK_CMPR,
  90
  91         /** Floating Point Status Register */
  92         MISCREG_FSR,
  93
  94         /** MMU Internal Registers */
  95         MISCREG_MMU_P_CONTEXT,
  96         MISCREG_MMU_S_CONTEXT, /* 40 */
  97         MISCREG_MMU_PART_ID,
  98         MISCREG_MMU_LSU_CTRL,
  99
 100         /** Scratchpad regiscers **/
 101         MISCREG_SCRATCHPAD_R0, /* 60 */
 102         MISCREG_SCRATCHPAD_R1,
 103         MISCREG_SCRATCHPAD_R2,
 104         MISCREG_SCRATCHPAD_R3,
 105         MISCREG_SCRATCHPAD_R4,
 106         MISCREG_SCRATCHPAD_R5,
 107         MISCREG_SCRATCHPAD_R6,
 108         MISCREG_SCRATCHPAD_R7,
 109
 110         /* CPU Queue Registers */
 111         MISCREG_QUEUE_CPU_MONDO_HEAD,
 112         MISCREG_QUEUE_CPU_MONDO_TAIL,
 113         MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
 114         MISCREG_QUEUE_DEV_MONDO_TAIL,
 115         MISCREG_QUEUE_RES_ERROR_HEAD,
 116         MISCREG_QUEUE_RES_ERROR_TAIL,
 117         MISCREG_QUEUE_NRES_ERROR_HEAD,
 118         MISCREG_QUEUE_NRES_ERROR_TAIL,
 119
 120         /* All the data for the TLB packed up in one register. */
 121         MISCREG_TLB_DATA,
 122         MISCREG_NUMMISCREGS
 123     };
 124
 125     struct HPSTATE {
 126         const static uint64_t id = 0x800;   // this impl. dependent (id) field m
 127         const static uint64_t ibe = 0x400;
 128         const static uint64_t red = 0x20;
 129         const static uint64_t hpriv = 0x4;
 130         const static uint64_t tlz = 0x1;
 131     };
 132
 133
 134     struct PSTATE {
 135         const static int cle = 0x200;
 136         const static int tle = 0x100;
 137         const static int mm = 0xC0;
 138         const static int pef = 0x10;
 139         const static int am = 0x8;
 140         const static int priv = 0x4;
 141         const static int ie = 0x2;
 142     };
 143
 144     struct STS {
 145         const static int st_idle     = 0x00;
 146         const static int st_wait     = 0x01;
 147         const static int st_halt     = 0x02;
 148         const static int st_run      = 0x05;
 149         const static int st_spec_run = 0x07;
 150         const static int st_spec_rdy = 0x13;
 151         const static int st_ready    = 0x19;
 152         const static int active      = 0x01;
 153         const static int speculative = 0x04;
 154         const static int shft_id     = 8;
 155         const static int shft_fsm0   = 31;
 156         const static int shft_fsm1   = 26;
 157         const static int shft_fsm2   = 21;
 158         const static int shft_fsm3   = 16;
 159     };
 160
 161
 162     const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
 163     const int NumMiscRegs = MISCREG_NUMMISCREGS;
 164
 165     // The control registers, broken out into fields
 166     class MiscRegFile
 167     {
 168       private:
 169
 170         /* ASR Registers */
 171         //uint64_t y;           // Y (used in obsolete multiplication)
 172         //uint8_t ccr;          // Condition Code Register
 173         uint8_t asi;            // Address Space Identifier
 174         uint64_t tick;          // Hardware clock-tick counter
 175         uint8_t fprs;           // Floating-Point Register State
 176         uint64_t gsr;           // General Status Register
 177         uint64_t softint;
 178         uint64_t tick_cmpr;     // Hardware tick compare registers
 179         uint64_t stick;         // Hardware clock-tick counter
 180         uint64_t stick_cmpr;    // Hardware tick compare registers
 181
 182
 183         /* Privileged Registers */
 184         uint64_t tpc[MaxTL];    // Trap Program Counter (value from
 185                                 // previous trap level)
 186         uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
 187                                 // previous trap level)
 188         uint64_t tstate[MaxTL]; // Trap State
 189         uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
 190                                 // on the previous level)
 191         uint64_t tba;           // Trap Base Address
 192
 193         uint16_t pstate;        // Process State Register
 194         uint8_t tl;             // Trap Level
 195         uint8_t pil;            // Process Interrupt Register
 196         uint8_t cwp;            // Current Window Pointer
 197         //uint8_t cansave;      // Savable windows
 198         //uint8_t canrestore;   // Restorable windows
 199         //uint8_t cleanwin;     // Clean windows
 200         //uint8_t otherwin;     // Other windows
 201         //uint8_t wstate;               // Window State
 202         uint8_t gl;             // Global level register
 203
 204         /** Hyperprivileged Registers */
 205         uint64_t hpstate;       // Hyperprivileged State Register
 206         uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
 207         uint64_t hintp;
 208         uint64_t htba;          // Hyperprivileged Trap Base Address register
 209         uint64_t hstick_cmpr;   // Hardware tick compare registers
 210
 211         uint64_t strandStatusReg;// Per strand status register
 212
 213         /** Floating point misc registers. */
 214         uint64_t fsr;           // Floating-Point State Register
 215
 216         /** MMU Internal Registers */
 217         uint16_t priContext;
 218         uint16_t secContext;
 219         uint16_t partId;
 220         uint64_t lsuCtrlReg;
 221
 222         uint64_t scratchPad[8];
 223
 224         uint64_t cpu_mondo_head;
 225         uint64_t cpu_mondo_tail;
 226         uint64_t dev_mondo_head;
 227         uint64_t dev_mondo_tail;
 228         uint64_t res_error_head;
 229         uint64_t res_error_tail;
 230         uint64_t nres_error_head;
 231         uint64_t nres_error_tail;
 232
 233         // These need to check the int_dis field and if 0 then
 234         // set appropriate bit in softint and checkinterrutps on the cpu
 235 #if FULL_SYSTEM
 236         void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
 237         MiscReg readFSReg(int miscReg, ThreadContext * tc);
 238
 239         // Update interrupt state on softint or pil change
 240         void checkSoftInt(ThreadContext *tc);
 241
 242         /** Process a tick compare event and generate an interrupt on the cpu if
 243          * appropriate. */
 244         void processTickCompare(ThreadContext *tc);
 245         void processSTickCompare(ThreadContext *tc);
 246         void processHSTickCompare(ThreadContext *tc);
 247
 248         typedef CpuEventWrapper<MiscRegFile,
 249                 &MiscRegFile::processTickCompare> TickCompareEvent;
 250         TickCompareEvent *tickCompare;
 251
 252         typedef CpuEventWrapper<MiscRegFile,
 253                 &MiscRegFile::processSTickCompare> STickCompareEvent;
 254         STickCompareEvent *sTickCompare;
 255
 256         typedef CpuEventWrapper<MiscRegFile,
 257                 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
 258         HSTickCompareEvent *hSTickCompare;
 259 #endif
 260       public:
 261
 262         void clear();
 263
 264         MiscRegFile()
 265         {
 266             clear();
 267         }
 268
 269         MiscReg readRegNoEffect(int miscReg);
 270
 271         MiscReg readReg(int miscReg, ThreadContext *tc);
 272
 273         void setRegNoEffect(int miscReg, const MiscReg &val);
 274
 275         void setReg(int miscReg,
 276                 const MiscReg &val, ThreadContext * tc);
 277
 278         int getInstAsid()
 279         {
 280             return priContext | (uint32_t)partId << 13;
 281         }
 282
 283         int getDataAsid()
 284         {
 285             return priContext | (uint32_t)partId << 13;
 286         }
 287
 288         void serialize(EventManager *em, std::ostream & os);
 289
 290         void unserialize(EventManager *em, Checkpoint *cp,
 291                          const std::string & section);
 292
 293         void copyMiscRegs(ThreadContext * tc);
 294
 295       protected:
 296
 297         bool isHyperPriv() { return (hpstate & (1 << 2)); }
 298         bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
 299         bool isNonPriv() { return !isPriv(); }
 300     };
 301 }
 302
 303 #endif