src/arch/sparc/miscregfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
  33 #define __ARCH_SPARC_MISCREGFILE_HH__
  34
  35 #include "arch/sparc/faults.hh"
  36 #include "arch/sparc/isa_traits.hh"
  37 #include "arch/sparc/types.hh"
  38
  39 #include <string>
  40
  41 namespace SparcISA
  42 {
  43
  44     //These functions map register indices to names
  45     std::string getMiscRegName(RegIndex);
  46
  47     const int AsrStart = 0;
  48     const int PrStart = 32;
  49     const int HprStart = 64;
  50     const int MiscStart = 96;
  51
  52     enum MiscRegIndex
  53     {
  54         /** Ancillary State Registers */
  55         MISCREG_Y  = AsrStart + 0,
  56         MISCREG_CCR = AsrStart + 2,
  57         MISCREG_ASI = AsrStart + 3,
  58         MISCREG_TICK = AsrStart + 4,
  59         MISCREG_PC = AsrStart + 5,
  60         MISCREG_FPRS = AsrStart + 6,
  61         MISCREG_PCR = AsrStart + 16,
  62         MISCREG_PIC = AsrStart + 17,
  63         MISCREG_GSR = AsrStart + 19,
  64         MISCREG_SOFTINT_SET = AsrStart + 20,
  65         MISCREG_SOFTINT_CLR = AsrStart + 21,
  66         MISCREG_SOFTINT = AsrStart + 22,
  67         MISCREG_TICK_CMPR = AsrStart + 23,
  68         MISCREG_STICK = AsrStart + 24,
  69         MISCREG_STICK_CMPR = AsrStart + 25,
  70
  71         /** Privilged Registers */
  72         MISCREG_TPC = PrStart + 0,
  73         MISCREG_TNPC = PrStart + 1,
  74         MISCREG_TSTATE = PrStart + 2,
  75         MISCREG_TT = PrStart + 3,
  76         MISCREG_PRIVTICK = PrStart + 4,
  77         MISCREG_TBA = PrStart + 5,
  78         MISCREG_PSTATE = PrStart + 6,
  79         MISCREG_TL = PrStart + 7,
  80         MISCREG_PIL = PrStart + 8,
  81         MISCREG_CWP = PrStart + 9,
  82         MISCREG_CANSAVE = PrStart + 10,
  83         MISCREG_CANRESTORE = PrStart + 11,
  84         MISCREG_CLEANWIN = PrStart + 12,
  85         MISCREG_OTHERWIN = PrStart + 13,
  86         MISCREG_WSTATE = PrStart + 14,
  87         MISCREG_GL = PrStart + 16,
  88
  89         /** Hyper privileged registers */
  90         MISCREG_HPSTATE = HprStart + 0,
  91         MISCREG_HTSTATE = HprStart + 1,
  92         MISCREG_HINTP = HprStart + 3,
  93         MISCREG_HTBA = HprStart + 5,
  94         MISCREG_HVER = HprStart + 6,
  95         MISCREG_STRAND_STS_REG = HprStart + 16,
  96         MISCREG_HSTICK_CMPR = HprStart + 31,
  97
  98         /** Floating Point Status Register */
  99         MISCREG_FSR = MiscStart + 0
 100
 101     };
 102
 103     // The control registers, broken out into fields
 104     class MiscRegFile
 105     {
 106       private:
 107
 108         /* ASR Registers */
 109         union {
 110             uint64_t y;         // Y (used in obsolete multiplication)
 111             struct {
 112                 uint64_t value:32;      // The actual value stored in y
 113                 uint64_t :32;   // reserved bits
 114             } yFields;
 115         };
 116         union {
 117             uint8_t     ccr;            // Condition Code Register
 118             struct {
 119                 union {
 120                     uint8_t icc:4;      // 32-bit condition codes
 121                     struct {
 122                         uint8_t c:1;    // Carry
 123                         uint8_t v:1;    // Overflow
 124                         uint8_t z:1;    // Zero
 125                         uint8_t n:1;    // Negative
 126                     } iccFields;
 127                 };
 128                 union {
 129                     uint8_t xcc:4;      // 64-bit condition codes
 130                     struct {
 131                         uint8_t c:1;    // Carry
 132                         uint8_t v:1;    // Overflow
 133                         uint8_t z:1;    // Zero
 134                         uint8_t n:1;    // Negative
 135                     } xccFields;
 136                 };
 137             } ccrFields;
 138         };
 139         uint8_t asi;            // Address Space Identifier
 140         union {
 141             uint64_t tick;              // Hardware clock-tick counter
 142             struct {
 143                 int64_t counter:63;     // Clock-tick count
 144                 uint64_t npt:1;         // Non-priveleged trap
 145             } tickFields;
 146         };
 147         union {
 148             uint8_t             fprs;   // Floating-Point Register State
 149             struct {
 150                 uint8_t dl:1;           // Dirty lower
 151                 uint8_t du:1;           // Dirty upper
 152                 uint8_t fef:1;          // FPRS enable floating-Point
 153             } fprsFields;
 154         };
 155         union {
 156             uint64_t gsr;               //General Status Register
 157             struct {
 158                 uint64_t mask:32;
 159                 uint64_t :4;
 160                 uint64_t im:1;
 161                 uint64_t irnd:2;
 162                 uint64_t :17;
 163                 uint64_t scale:5;
 164                 uint64_t align:3;
 165             } gsrFields;
 166         };
 167         union {
 168             uint64_t softint;
 169             struct {
 170                 uint64_t tm:1;
 171                 uint64_t int_level:14;
 172                 uint64_t sm:1;
 173             } softintFields;
 174         };
 175         union {
 176             uint64_t tick_cmpr;         // Hardware tick compare registers
 177             struct {
 178                 uint64_t tick_cmpr:63;  // Clock-tick count
 179                 uint64_t int_dis:1;             // Non-priveleged trap
 180             } tick_cmprFields;
 181         };
 182         union {
 183             uint64_t stick;             // Hardware clock-tick counter
 184             struct {
 185                 int64_t :63;    // Not used, storage in SparcSystem
 186                 uint64_t npt:1;         // Non-priveleged trap
 187             } stickFields;
 188         };
 189         union {
 190             uint64_t stick_cmpr;                // Hardware tick compare registers
 191             struct {
 192                 uint64_t tick_cmpr:63;  // Clock-tick count
 193                 uint64_t int_dis:1;             // Non-priveleged trap
 194             } stick_cmprFields;
 195         };
 196
 197
 198         /* Privileged Registers */
 199         uint64_t tpc[MaxTL];    // Trap Program Counter (value from
 200                                 // previous trap level)
 201         uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
 202                                 // previous trap level)
 203         union {
 204             uint64_t tstate[MaxTL];     // Trap State
 205             struct {
 206                 //Values are from previous trap level
 207                 uint64_t cwp:5;         // Current Window Pointer
 208                 uint64_t :3;    // Reserved bits
 209                 uint64_t pstate:13;     // Process State
 210                 uint64_t :3;    // Reserved bits
 211                 uint64_t asi:8;         // Address Space Identifier
 212                 uint64_t ccr:8;         // Condition Code Register
 213                 uint64_t gl:8;          // Global level
 214             } tstateFields[MaxTL];
 215         };
 216         uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
 217                                 // on the previous level)
 218         uint64_t tba;           // Trap Base Address
 219
 220         union {
 221             uint16_t pstate;            // Process State Register
 222             struct {
 223                 uint16_t :1;            // reserved
 224                 uint16_t ie:1;          // Interrupt enable
 225                 uint16_t priv:1;        // Privelege mode
 226                 uint16_t am:1;          // Address mask
 227                 uint16_t pef:1;         // PSTATE enable floating-point
 228                 uint16_t :1;            // reserved2
 229                 uint16_t mm:2;          // Memory Model
 230                 uint16_t tle:1;         // Trap little-endian
 231                 uint16_t cle:1;         // Current little-endian
 232             } pstateFields;
 233         };
 234         uint8_t tl;             // Trap Level
 235         uint8_t pil;            // Process Interrupt Register
 236         uint8_t cwp;            // Current Window Pointer
 237         uint8_t cansave;        // Savable windows
 238         uint8_t canrestore;     // Restorable windows
 239         uint8_t cleanwin;       // Clean windows
 240         uint8_t otherwin;       // Other windows
 241         union {
 242             uint8_t wstate;             // Window State
 243             struct {
 244                 uint8_t normal:3;       // Bits TT<4:2> are set to on a normal
 245                                         // register window trap
 246                 uint8_t other:3;        // Bits TT<4:2> are set to on an "otherwin"
 247                                         // register window trap
 248             } wstateFields;
 249         };
 250         uint8_t gl;             // Global level register
 251
 252
 253         /** Hyperprivileged Registers */
 254         union {
 255             uint64_t hpstate; // Hyperprivileged State Register
 256             struct {
 257                 uint8_t tlz: 1;
 258                 uint8_t :1;
 259                 uint8_t hpriv:1;
 260                 uint8_t :2;
 261                 uint8_t red:1;
 262                 uint8_t :4;
 263                 uint8_t ibe:1;
 264                 uint8_t id:1;
 265             } hpstateFields;
 266         };
 267
 268         uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
 269         uint64_t hintp;
 270         uint64_t htba; // Hyperprivileged Trap Base Address register
 271         union {
 272             uint64_t hstick_cmpr;               // Hardware tick compare registers
 273             struct {
 274                 uint64_t tick_cmpr:63;  // Clock-tick count
 275                 uint64_t int_dis:1;             // Non-priveleged trap
 276             } hstick_cmprFields;
 277         };
 278
 279         uint64_t strandStatusReg; // Per strand status register
 280
 281
 282         /** Floating point misc registers. */
 283         union {
 284             uint64_t    fsr;    // Floating-Point State Register
 285             struct {
 286                 union {
 287                     uint64_t cexc:5;    // Current excpetion
 288                     struct {
 289                         uint64_t nxc:1;         // Inexact
 290                         uint64_t dzc:1;         // Divide by zero
 291                         uint64_t ufc:1;         // Underflow
 292                         uint64_t ofc:1;         // Overflow
 293                         uint64_t nvc:1;         // Invalid operand
 294                     } cexcFields;
 295                 };
 296                 union {
 297                     uint64_t aexc:5;            // Accrued exception
 298                     struct {
 299                         uint64_t nxc:1;         // Inexact
 300                         uint64_t dzc:1;         // Divide by zero
 301                         uint64_t ufc:1;         // Underflow
 302                         uint64_t ofc:1;         // Overflow
 303                         uint64_t nvc:1;         // Invalid operand
 304                     } aexcFields;
 305                 };
 306                 uint64_t fcc0:2;                // Floating-Point condtion codes
 307                 uint64_t :1;            // Reserved bits
 308                 uint64_t qne:1;                 // Deferred trap queue not empty
 309                                                 // with no queue, it should read 0
 310                 uint64_t ftt:3;                 // Floating-Point trap type
 311                 uint64_t ver:3;                 // Version (of the FPU)
 312                 uint64_t :2;            // Reserved bits
 313                 uint64_t ns:1;                  // Nonstandard floating point
 314                 union {
 315                     uint64_t tem:5;                     // Trap Enable Mask
 316                     struct {
 317                         uint64_t nxm:1;         // Inexact
 318                         uint64_t dzm:1;         // Divide by zero
 319                         uint64_t ufm:1;         // Underflow
 320                         uint64_t ofm:1;         // Overflow
 321                         uint64_t nvm:1;         // Invalid operand
 322                     } temFields;
 323                 };
 324                 uint64_t :2;            // Reserved bits
 325                 uint64_t rd:2;                  // Rounding direction
 326                 uint64_t fcc1:2;                // Floating-Point condition codes
 327                 uint64_t fcc2:2;                // Floating-Point condition codes
 328                 uint64_t fcc3:2;                // Floating-Point condition codes
 329                 uint64_t :26;           // Reserved bits
 330             } fsrFields;
 331         };
 332
 333         // These need to check the int_dis field and if 0 then
 334         // set appropriate bit in softint and checkinterrutps on the cpu
 335 #if FULL_SYSTEM
 336         /** Process a tick compare event and generate an interrupt on the cpu if
 337          * appropriate. */
 338         void processTickCompare(ThreadContext *tc);
 339         void processSTickCompare(ThreadContext *tc);
 340         void processHSTickCompare(ThreadContext *tc);
 341
 342         typedef CpuEventWrapper<MiscRegFile,
 343                 &MiscRegFile::processTickCompare> TickCompareEvent;
 344         TickCompareEvent *tickCompare;
 345
 346         typedef CpuEventWrapper<MiscRegFile,
 347                 &MiscRegFile::processSTickCompare> STickCompareEvent;
 348         STickCompareEvent *sTickCompare;
 349
 350         typedef CpuEventWrapper<MiscRegFile,
 351                 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
 352         HSTickCompareEvent *hSTickCompare;
 353
 354         /** Fullsystem only register version of ReadRegWithEffect() */
 355         MiscReg readFSRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
 356         /** Fullsystem only register version of SetRegWithEffect() */
 357         Fault setFSRegWithEffect(int miscReg, const MiscReg &val,
 358                 ThreadContext * tc);
 359 #endif
 360       public:
 361
 362         void reset();
 363
 364         MiscRegFile()
 365         {
 366             reset();
 367         }
 368
 369         /** read a value out of an either an SE or FS IPR. No checking is done
 370          * about SE vs. FS as this is mostly used to copy the regfile. Thus more
 371          * register are copied that are necessary for FS. However this prevents
 372          * a bunch of ifdefs and is rarely called so is not performance
 373          * criticial. */
 374         MiscReg readReg(int miscReg);
 375
 376         /** Read a value from an IPR. Only the SE iprs are here and the rest
 377          * are are readFSRegWithEffect (which is called by readRegWithEffect()).
 378          * Checking is done for permission based on state bits in the miscreg
 379          * file. */
 380         MiscReg readRegWithEffect(int miscReg, Fault &fault, ThreadContext *tc);
 381
 382         /** write a value into an either an SE or FS IPR. No checking is done
 383          * about SE vs. FS as this is mostly used to copy the regfile. Thus more
 384          * register are copied that are necessary for FS. However this prevents
 385          * a bunch of ifdefs and is rarely called so is not performance
 386          * criticial.*/
 387         Fault setReg(int miscReg, const MiscReg &val);
 388
 389         /** Write a value into an IPR. Only the SE iprs are here and the rest
 390          * are are setFSRegWithEffect (which is called by setRegWithEffect()).
 391          * Checking is done for permission based on state bits in the miscreg
 392          * file. */
 393         Fault setRegWithEffect(int miscReg,
 394                 const MiscReg &val, ThreadContext * tc);
 395
 396         void serialize(std::ostream & os);
 397
 398         void unserialize(Checkpoint * cp, const std::string & section);
 399
 400         void copyMiscRegs(ThreadContext * tc);
 401
 402       protected:
 403
 404         bool isHyperPriv() { return hpstateFields.hpriv; }
 405         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
 406         bool isNonPriv() { return !isPriv(); }
 407     };
 408 }
 409
 410 #endif