src/arch/sparc/miscregfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
  33 #define __ARCH_SPARC_MISCREGFILE_HH__
  34
  35 #include "arch/sparc/faults.hh"
  36 #include "arch/sparc/isa_traits.hh"
  37 #include "arch/sparc/types.hh"
  38 #include "cpu/cpuevent.hh"
  39
  40 #include <string>
  41
  42 class Checkpoint;
  43
  44 namespace SparcISA
  45 {
  46     //These functions map register indices to names
  47     std::string getMiscRegName(RegIndex);
  48
  49     enum MiscRegIndex
  50     {
  51         /** Ancillary State Registers */
  52 //        MISCREG_Y,
  53 //        MISCREG_CCR,
  54         MISCREG_ASI,
  55         MISCREG_TICK,
  56         MISCREG_FPRS,
  57         MISCREG_PCR,
  58         MISCREG_PIC,
  59         MISCREG_GSR,
  60         MISCREG_SOFTINT_SET,
  61         MISCREG_SOFTINT_CLR,
  62         MISCREG_SOFTINT, /* 10 */
  63         MISCREG_TICK_CMPR,
  64         MISCREG_STICK,
  65         MISCREG_STICK_CMPR,
  66
  67         /** Privilged Registers */
  68         MISCREG_TPC,
  69         MISCREG_TNPC,
  70         MISCREG_TSTATE,
  71         MISCREG_TT,
  72         MISCREG_PRIVTICK,
  73         MISCREG_TBA,
  74         MISCREG_PSTATE, /* 20 */
  75         MISCREG_TL,
  76         MISCREG_PIL,
  77         MISCREG_CWP,
  78 //        MISCREG_CANSAVE,
  79 //        MISCREG_CANRESTORE,
  80 //        MISCREG_CLEANWIN,
  81 //        MISCREG_OTHERWIN,
  82 //        MISCREG_WSTATE,
  83         MISCREG_GL,
  84
  85         /** Hyper privileged registers */
  86         MISCREG_HPSTATE, /* 30 */
  87         MISCREG_HTSTATE,
  88         MISCREG_HINTP,
  89         MISCREG_HTBA,
  90         MISCREG_HVER,
  91         MISCREG_STRAND_STS_REG,
  92         MISCREG_HSTICK_CMPR,
  93
  94         /** Floating Point Status Register */
  95         MISCREG_FSR,
  96
  97         /** MMU Internal Registers */
  98         MISCREG_MMU_P_CONTEXT,
  99         MISCREG_MMU_S_CONTEXT, /* 40 */
 100         MISCREG_MMU_PART_ID,
 101         MISCREG_MMU_LSU_CTRL,
 102
 103         MISCREG_MMU_ITLB_C0_TSB_PS0,
 104         MISCREG_MMU_ITLB_C0_TSB_PS1,
 105         MISCREG_MMU_ITLB_C0_CONFIG,
 106         MISCREG_MMU_ITLB_CX_TSB_PS0,
 107         MISCREG_MMU_ITLB_CX_TSB_PS1,
 108         MISCREG_MMU_ITLB_CX_CONFIG,
 109         MISCREG_MMU_ITLB_SFSR,
 110         MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
 111
 112         MISCREG_MMU_DTLB_C0_TSB_PS0,
 113         MISCREG_MMU_DTLB_C0_TSB_PS1,
 114         MISCREG_MMU_DTLB_C0_CONFIG,
 115         MISCREG_MMU_DTLB_CX_TSB_PS0,
 116         MISCREG_MMU_DTLB_CX_TSB_PS1,
 117         MISCREG_MMU_DTLB_CX_CONFIG,
 118         MISCREG_MMU_DTLB_SFSR,
 119         MISCREG_MMU_DTLB_SFAR,
 120         MISCREG_MMU_DTLB_TAG_ACCESS,
 121
 122         /** Scratchpad regiscers **/
 123         MISCREG_SCRATCHPAD_R0, /* 60 */
 124         MISCREG_SCRATCHPAD_R1,
 125         MISCREG_SCRATCHPAD_R2,
 126         MISCREG_SCRATCHPAD_R3,
 127         MISCREG_SCRATCHPAD_R4,
 128         MISCREG_SCRATCHPAD_R5,
 129         MISCREG_SCRATCHPAD_R6,
 130         MISCREG_SCRATCHPAD_R7,
 131
 132         /* CPU Queue Registers */
 133         MISCREG_QUEUE_CPU_MONDO_HEAD,
 134         MISCREG_QUEUE_CPU_MONDO_TAIL,
 135         MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
 136         MISCREG_QUEUE_DEV_MONDO_TAIL,
 137         MISCREG_QUEUE_RES_ERROR_HEAD,
 138         MISCREG_QUEUE_RES_ERROR_TAIL,
 139         MISCREG_QUEUE_NRES_ERROR_HEAD,
 140         MISCREG_QUEUE_NRES_ERROR_TAIL,
 141
 142         /* All the data for the TLB packed up in one register. */
 143         MISCREG_TLB_DATA,
 144         MISCREG_NUMMISCREGS
 145     };
 146
 147     struct HPSTATE {
 148         const static uint64_t id = 0x800;   // this impl. dependent (id) field m
 149         const static uint64_t ibe = 0x400;
 150         const static uint64_t red = 0x20;
 151         const static uint64_t hpriv = 0x4;
 152         const static uint64_t tlz = 0x1;
 153     };
 154
 155
 156     struct PSTATE {
 157         const static int cle = 0x200;
 158         const static int tle = 0x100;
 159         const static int mm = 0xC0;
 160         const static int pef = 0x10;
 161         const static int am = 0x8;
 162         const static int priv = 0x4;
 163         const static int ie = 0x2;
 164     };
 165
 166     struct STS {
 167         const static int st_idle     = 0x00;
 168         const static int st_wait     = 0x01;
 169         const static int st_halt     = 0x02;
 170         const static int st_run      = 0x05;
 171         const static int st_spec_run = 0x07;
 172         const static int st_spec_rdy = 0x13;
 173         const static int st_ready    = 0x19;
 174         const static int active      = 0x01;
 175         const static int speculative = 0x04;
 176         const static int shft_id     = 8;
 177         const static int shft_fsm0   = 31;
 178         const static int shft_fsm1   = 26;
 179         const static int shft_fsm2   = 21;
 180         const static int shft_fsm3   = 16;
 181     };
 182
 183
 184     const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
 185     const int NumMiscRegs = MISCREG_NUMMISCREGS;
 186
 187     // The control registers, broken out into fields
 188     class MiscRegFile
 189     {
 190       private:
 191
 192         /* ASR Registers */
 193         //uint64_t y;           // Y (used in obsolete multiplication)
 194         //uint8_t ccr;          // Condition Code Register
 195         uint8_t asi;            // Address Space Identifier
 196         uint64_t tick;          // Hardware clock-tick counter
 197         uint8_t fprs;           // Floating-Point Register State
 198         uint64_t gsr;           // General Status Register
 199         uint64_t softint;
 200         uint64_t tick_cmpr;     // Hardware tick compare registers
 201         uint64_t stick;         // Hardware clock-tick counter
 202         uint64_t stick_cmpr;    // Hardware tick compare registers
 203
 204
 205         /* Privileged Registers */
 206         uint64_t tpc[MaxTL];    // Trap Program Counter (value from
 207                                 // previous trap level)
 208         uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
 209                                 // previous trap level)
 210         uint64_t tstate[MaxTL]; // Trap State
 211         uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
 212                                 // on the previous level)
 213         uint64_t tba;           // Trap Base Address
 214
 215         uint16_t pstate;        // Process State Register
 216         uint8_t tl;             // Trap Level
 217         uint8_t pil;            // Process Interrupt Register
 218         uint8_t cwp;            // Current Window Pointer
 219         //uint8_t cansave;      // Savable windows
 220         //uint8_t canrestore;   // Restorable windows
 221         //uint8_t cleanwin;     // Clean windows
 222         //uint8_t otherwin;     // Other windows
 223         //uint8_t wstate;               // Window State
 224         uint8_t gl;             // Global level register
 225
 226         /** Hyperprivileged Registers */
 227         uint64_t hpstate;       // Hyperprivileged State Register
 228         uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
 229         uint64_t hintp;
 230         uint64_t htba;          // Hyperprivileged Trap Base Address register
 231         uint64_t hstick_cmpr;   // Hardware tick compare registers
 232
 233         uint64_t strandStatusReg;// Per strand status register
 234
 235         /** Floating point misc registers. */
 236         uint64_t fsr;           // Floating-Point State Register
 237
 238         /** MMU Internal Registers */
 239         uint16_t priContext;
 240         uint16_t secContext;
 241         uint16_t partId;
 242         uint64_t lsuCtrlReg;
 243
 244         uint64_t iTlbC0TsbPs0;
 245         uint64_t iTlbC0TsbPs1;
 246         uint64_t iTlbC0Config;
 247         uint64_t iTlbCXTsbPs0;
 248         uint64_t iTlbCXTsbPs1;
 249         uint64_t iTlbCXConfig;
 250         uint64_t iTlbSfsr;
 251         uint64_t iTlbTagAccess;
 252
 253         uint64_t dTlbC0TsbPs0;
 254         uint64_t dTlbC0TsbPs1;
 255         uint64_t dTlbC0Config;
 256         uint64_t dTlbCXTsbPs0;
 257         uint64_t dTlbCXTsbPs1;
 258         uint64_t dTlbCXConfig;
 259         uint64_t dTlbSfsr;
 260         uint64_t dTlbSfar;
 261         uint64_t dTlbTagAccess;
 262
 263         uint64_t scratchPad[8];
 264
 265         uint64_t cpu_mondo_head;
 266         uint64_t cpu_mondo_tail;
 267         uint64_t dev_mondo_head;
 268         uint64_t dev_mondo_tail;
 269         uint64_t res_error_head;
 270         uint64_t res_error_tail;
 271         uint64_t nres_error_head;
 272         uint64_t nres_error_tail;
 273
 274         // These need to check the int_dis field and if 0 then
 275         // set appropriate bit in softint and checkinterrutps on the cpu
 276 #if FULL_SYSTEM
 277         void  setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
 278         MiscReg readFSReg(int miscReg, ThreadContext * tc);
 279
 280         // Update interrupt state on softint or pil change
 281         void checkSoftInt(ThreadContext *tc);
 282
 283         /** Process a tick compare event and generate an interrupt on the cpu if
 284          * appropriate. */
 285         void processTickCompare(ThreadContext *tc);
 286         void processSTickCompare(ThreadContext *tc);
 287         void processHSTickCompare(ThreadContext *tc);
 288
 289         typedef CpuEventWrapper<MiscRegFile,
 290                 &MiscRegFile::processTickCompare> TickCompareEvent;
 291         TickCompareEvent *tickCompare;
 292
 293         typedef CpuEventWrapper<MiscRegFile,
 294                 &MiscRegFile::processSTickCompare> STickCompareEvent;
 295         STickCompareEvent *sTickCompare;
 296
 297         typedef CpuEventWrapper<MiscRegFile,
 298                 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
 299         HSTickCompareEvent *hSTickCompare;
 300 #endif
 301       public:
 302
 303         void clear();
 304
 305         MiscRegFile()
 306         {
 307             clear();
 308         }
 309
 310         MiscReg readRegNoEffect(int miscReg);
 311
 312         MiscReg readReg(int miscReg, ThreadContext *tc);
 313
 314         void setRegNoEffect(int miscReg, const MiscReg &val);
 315
 316         void setReg(int miscReg,
 317                 const MiscReg &val, ThreadContext * tc);
 318
 319         int getInstAsid()
 320         {
 321             return priContext | (uint32_t)partId << 13;
 322         }
 323
 324         int getDataAsid()
 325         {
 326             return priContext | (uint32_t)partId << 13;
 327         }
 328
 329         void serialize(std::ostream & os);
 330
 331         void unserialize(Checkpoint * cp, const std::string & section);
 332
 333         void copyMiscRegs(ThreadContext * tc);
 334
 335       protected:
 336
 337         bool isHyperPriv() { return (hpstate & (1 << 2)); }
 338         bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
 339         bool isNonPriv() { return !isPriv(); }
 340     };
 341 }
 342
 343 #endif