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32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
33 #define __ARCH_SPARC_MISCREGFILE_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "arch/sparc/types.hh"
38 #include "cpu/cpuevent.hh"
46 //These functions map register indices to names
47 std::string getMiscRegName(RegIndex);
51 /** Ancillary State Registers */
62 MISCREG_SOFTINT, /* 10 */
67 /** Privilged Registers */
74 MISCREG_PSTATE, /* 20 */
79 // MISCREG_CANRESTORE,
85 /** Hyper privileged registers */
86 MISCREG_HPSTATE, /* 30 */
91 MISCREG_STRAND_STS_REG,
94 /** Floating Point Status Register */
97 /** MMU Internal Registers */
98 MISCREG_MMU_P_CONTEXT,
99 MISCREG_MMU_S_CONTEXT, /* 40 */
101 MISCREG_MMU_LSU_CTRL,
103 MISCREG_MMU_ITLB_C0_TSB_PS0,
104 MISCREG_MMU_ITLB_C0_TSB_PS1,
105 MISCREG_MMU_ITLB_C0_CONFIG,
106 MISCREG_MMU_ITLB_CX_TSB_PS0,
107 MISCREG_MMU_ITLB_CX_TSB_PS1,
108 MISCREG_MMU_ITLB_CX_CONFIG,
109 MISCREG_MMU_ITLB_SFSR,
110 MISCREG_MMU_ITLB_TAG_ACCESS, /* 50 */
112 MISCREG_MMU_DTLB_C0_TSB_PS0,
113 MISCREG_MMU_DTLB_C0_TSB_PS1,
114 MISCREG_MMU_DTLB_C0_CONFIG,
115 MISCREG_MMU_DTLB_CX_TSB_PS0,
116 MISCREG_MMU_DTLB_CX_TSB_PS1,
117 MISCREG_MMU_DTLB_CX_CONFIG,
118 MISCREG_MMU_DTLB_SFSR,
119 MISCREG_MMU_DTLB_SFAR,
120 MISCREG_MMU_DTLB_TAG_ACCESS,
122 /** Scratchpad regiscers **/
123 MISCREG_SCRATCHPAD_R0, /* 60 */
124 MISCREG_SCRATCHPAD_R1,
125 MISCREG_SCRATCHPAD_R2,
126 MISCREG_SCRATCHPAD_R3,
127 MISCREG_SCRATCHPAD_R4,
128 MISCREG_SCRATCHPAD_R5,
129 MISCREG_SCRATCHPAD_R6,
130 MISCREG_SCRATCHPAD_R7,
132 /* CPU Queue Registers */
133 MISCREG_QUEUE_CPU_MONDO_HEAD,
134 MISCREG_QUEUE_CPU_MONDO_TAIL,
135 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
136 MISCREG_QUEUE_DEV_MONDO_TAIL,
137 MISCREG_QUEUE_RES_ERROR_HEAD,
138 MISCREG_QUEUE_RES_ERROR_TAIL,
139 MISCREG_QUEUE_NRES_ERROR_HEAD,
140 MISCREG_QUEUE_NRES_ERROR_TAIL,
142 /* All the data for the TLB packed up in one register. */
148 const static uint64_t id = 0x800; // this impl. dependent (id) field m
149 const static uint64_t ibe = 0x400;
150 const static uint64_t red = 0x20;
151 const static uint64_t hpriv = 0x4;
152 const static uint64_t tlz = 0x1;
157 const static int cle = 0x200;
158 const static int tle = 0x100;
159 const static int mm = 0xC0;
160 const static int pef = 0x10;
161 const static int am = 0x8;
162 const static int priv = 0x4;
163 const static int ie = 0x2;
167 const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
168 const int NumMiscRegs = MISCREG_NUMMISCREGS;
170 // The control registers, broken out into fields
176 //uint64_t y; // Y (used in obsolete multiplication)
177 //uint8_t ccr; // Condition Code Register
178 uint8_t asi; // Address Space Identifier
179 uint64_t tick; // Hardware clock-tick counter
180 uint8_t fprs; // Floating-Point Register State
181 uint64_t gsr; // General Status Register
183 uint64_t tick_cmpr; // Hardware tick compare registers
184 uint64_t stick; // Hardware clock-tick counter
185 uint64_t stick_cmpr; // Hardware tick compare registers
188 /* Privileged Registers */
189 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
190 // previous trap level)
191 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
192 // previous trap level)
193 uint64_t tstate[MaxTL]; // Trap State
194 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
195 // on the previous level)
196 uint64_t tba; // Trap Base Address
198 uint16_t pstate; // Process State Register
199 uint8_t tl; // Trap Level
200 uint8_t pil; // Process Interrupt Register
201 uint8_t cwp; // Current Window Pointer
202 //uint8_t cansave; // Savable windows
203 //uint8_t canrestore; // Restorable windows
204 //uint8_t cleanwin; // Clean windows
205 //uint8_t otherwin; // Other windows
206 //uint8_t wstate; // Window State
207 uint8_t gl; // Global level register
209 /** Hyperprivileged Registers */
210 uint64_t hpstate; // Hyperprivileged State Register
211 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
213 uint64_t htba; // Hyperprivileged Trap Base Address register
214 uint64_t hstick_cmpr; // Hardware tick compare registers
216 uint64_t strandStatusReg;// Per strand status register
218 /** Floating point misc registers. */
219 uint64_t fsr; // Floating-Point State Register
221 /** MMU Internal Registers */
227 uint64_t iTlbC0TsbPs0;
228 uint64_t iTlbC0TsbPs1;
229 uint64_t iTlbC0Config;
230 uint64_t iTlbCXTsbPs0;
231 uint64_t iTlbCXTsbPs1;
232 uint64_t iTlbCXConfig;
234 uint64_t iTlbTagAccess;
236 uint64_t dTlbC0TsbPs0;
237 uint64_t dTlbC0TsbPs1;
238 uint64_t dTlbC0Config;
239 uint64_t dTlbCXTsbPs0;
240 uint64_t dTlbCXTsbPs1;
241 uint64_t dTlbCXConfig;
244 uint64_t dTlbTagAccess;
246 uint64_t scratchPad[8];
248 uint64_t cpu_mondo_head;
249 uint64_t cpu_mondo_tail;
250 uint64_t dev_mondo_head;
251 uint64_t dev_mondo_tail;
252 uint64_t res_error_head;
253 uint64_t res_error_tail;
254 uint64_t nres_error_head;
255 uint64_t nres_error_tail;
257 // These need to check the int_dis field and if 0 then
258 // set appropriate bit in softint and checkinterrutps on the cpu
260 void setFSRegWithEffect(int miscReg, const MiscReg &val,
262 MiscReg readFSRegWithEffect(int miscReg, ThreadContext * tc);
264 // Update interrupt state on softint or pil change
265 void checkSoftInt(ThreadContext *tc);
267 /** Process a tick compare event and generate an interrupt on the cpu if
269 void processTickCompare(ThreadContext *tc);
270 void processSTickCompare(ThreadContext *tc);
271 void processHSTickCompare(ThreadContext *tc);
273 typedef CpuEventWrapper<MiscRegFile,
274 &MiscRegFile::processTickCompare> TickCompareEvent;
275 TickCompareEvent *tickCompare;
277 typedef CpuEventWrapper<MiscRegFile,
278 &MiscRegFile::processSTickCompare> STickCompareEvent;
279 STickCompareEvent *sTickCompare;
281 typedef CpuEventWrapper<MiscRegFile,
282 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
283 HSTickCompareEvent *hSTickCompare;
294 MiscReg readReg(int miscReg);
296 MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
298 void setReg(int miscReg, const MiscReg &val);
300 void setRegWithEffect(int miscReg,
301 const MiscReg &val, ThreadContext * tc);
305 return priContext | (uint32_t)partId << 13;
310 return priContext | (uint32_t)partId << 13;
313 void serialize(std::ostream & os);
315 void unserialize(Checkpoint * cp, const std::string & section);
317 void copyMiscRegs(ThreadContext * tc);
321 bool isHyperPriv() { return (hpstate & (1 << 2)); }
322 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
323 bool isNonPriv() { return !isPriv(); }