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32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
33 #define __ARCH_SPARC_MISCREGFILE_HH__
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/isa_traits.hh"
37 #include "arch/sparc/types.hh"
38 #include "cpu/cpuevent.hh"
46 //These functions map register indices to names
47 std::string getMiscRegName(RegIndex);
51 /** Ancillary State Registers */
62 MISCREG_SOFTINT, /* 10 */
67 /** Privilged Registers */
74 MISCREG_PSTATE, /* 20 */
79 // MISCREG_CANRESTORE,
85 /** Hyper privileged registers */
86 MISCREG_HPSTATE, /* 30 */
91 MISCREG_STRAND_STS_REG,
94 /** Floating Point Status Register */
97 /** MMU Internal Registers */
98 MISCREG_MMU_P_CONTEXT,
99 MISCREG_MMU_S_CONTEXT, /* 40 */
101 MISCREG_MMU_LSU_CTRL,
103 /** Scratchpad regiscers **/
104 MISCREG_SCRATCHPAD_R0, /* 60 */
105 MISCREG_SCRATCHPAD_R1,
106 MISCREG_SCRATCHPAD_R2,
107 MISCREG_SCRATCHPAD_R3,
108 MISCREG_SCRATCHPAD_R4,
109 MISCREG_SCRATCHPAD_R5,
110 MISCREG_SCRATCHPAD_R6,
111 MISCREG_SCRATCHPAD_R7,
113 /* CPU Queue Registers */
114 MISCREG_QUEUE_CPU_MONDO_HEAD,
115 MISCREG_QUEUE_CPU_MONDO_TAIL,
116 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
117 MISCREG_QUEUE_DEV_MONDO_TAIL,
118 MISCREG_QUEUE_RES_ERROR_HEAD,
119 MISCREG_QUEUE_RES_ERROR_TAIL,
120 MISCREG_QUEUE_NRES_ERROR_HEAD,
121 MISCREG_QUEUE_NRES_ERROR_TAIL,
123 /* All the data for the TLB packed up in one register. */
129 const static uint64_t id = 0x800; // this impl. dependent (id) field m
130 const static uint64_t ibe = 0x400;
131 const static uint64_t red = 0x20;
132 const static uint64_t hpriv = 0x4;
133 const static uint64_t tlz = 0x1;
138 const static int cle = 0x200;
139 const static int tle = 0x100;
140 const static int mm = 0xC0;
141 const static int pef = 0x10;
142 const static int am = 0x8;
143 const static int priv = 0x4;
144 const static int ie = 0x2;
148 const static int st_idle = 0x00;
149 const static int st_wait = 0x01;
150 const static int st_halt = 0x02;
151 const static int st_run = 0x05;
152 const static int st_spec_run = 0x07;
153 const static int st_spec_rdy = 0x13;
154 const static int st_ready = 0x19;
155 const static int active = 0x01;
156 const static int speculative = 0x04;
157 const static int shft_id = 8;
158 const static int shft_fsm0 = 31;
159 const static int shft_fsm1 = 26;
160 const static int shft_fsm2 = 21;
161 const static int shft_fsm3 = 16;
165 const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
166 const int NumMiscRegs = MISCREG_NUMMISCREGS;
168 // The control registers, broken out into fields
174 //uint64_t y; // Y (used in obsolete multiplication)
175 //uint8_t ccr; // Condition Code Register
176 uint8_t asi; // Address Space Identifier
177 uint64_t tick; // Hardware clock-tick counter
178 uint8_t fprs; // Floating-Point Register State
179 uint64_t gsr; // General Status Register
181 uint64_t tick_cmpr; // Hardware tick compare registers
182 uint64_t stick; // Hardware clock-tick counter
183 uint64_t stick_cmpr; // Hardware tick compare registers
186 /* Privileged Registers */
187 uint64_t tpc[MaxTL]; // Trap Program Counter (value from
188 // previous trap level)
189 uint64_t tnpc[MaxTL]; // Trap Next Program Counter (value from
190 // previous trap level)
191 uint64_t tstate[MaxTL]; // Trap State
192 uint16_t tt[MaxTL]; // Trap Type (Type of trap which occured
193 // on the previous level)
194 uint64_t tba; // Trap Base Address
196 uint16_t pstate; // Process State Register
197 uint8_t tl; // Trap Level
198 uint8_t pil; // Process Interrupt Register
199 uint8_t cwp; // Current Window Pointer
200 //uint8_t cansave; // Savable windows
201 //uint8_t canrestore; // Restorable windows
202 //uint8_t cleanwin; // Clean windows
203 //uint8_t otherwin; // Other windows
204 //uint8_t wstate; // Window State
205 uint8_t gl; // Global level register
207 /** Hyperprivileged Registers */
208 uint64_t hpstate; // Hyperprivileged State Register
209 uint64_t htstate[MaxTL];// Hyperprivileged Trap State Register
211 uint64_t htba; // Hyperprivileged Trap Base Address register
212 uint64_t hstick_cmpr; // Hardware tick compare registers
214 uint64_t strandStatusReg;// Per strand status register
216 /** Floating point misc registers. */
217 uint64_t fsr; // Floating-Point State Register
219 /** MMU Internal Registers */
225 uint64_t scratchPad[8];
227 uint64_t cpu_mondo_head;
228 uint64_t cpu_mondo_tail;
229 uint64_t dev_mondo_head;
230 uint64_t dev_mondo_tail;
231 uint64_t res_error_head;
232 uint64_t res_error_tail;
233 uint64_t nres_error_head;
234 uint64_t nres_error_tail;
236 // These need to check the int_dis field and if 0 then
237 // set appropriate bit in softint and checkinterrutps on the cpu
239 void setFSReg(int miscReg, const MiscReg &val, ThreadContext *tc);
240 MiscReg readFSReg(int miscReg, ThreadContext * tc);
242 // Update interrupt state on softint or pil change
243 void checkSoftInt(ThreadContext *tc);
245 /** Process a tick compare event and generate an interrupt on the cpu if
247 void processTickCompare(ThreadContext *tc);
248 void processSTickCompare(ThreadContext *tc);
249 void processHSTickCompare(ThreadContext *tc);
251 typedef CpuEventWrapper<MiscRegFile,
252 &MiscRegFile::processTickCompare> TickCompareEvent;
253 TickCompareEvent *tickCompare;
255 typedef CpuEventWrapper<MiscRegFile,
256 &MiscRegFile::processSTickCompare> STickCompareEvent;
257 STickCompareEvent *sTickCompare;
259 typedef CpuEventWrapper<MiscRegFile,
260 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
261 HSTickCompareEvent *hSTickCompare;
272 MiscReg readRegNoEffect(int miscReg);
274 MiscReg readReg(int miscReg, ThreadContext *tc);
276 void setRegNoEffect(int miscReg, const MiscReg &val);
278 void setReg(int miscReg,
279 const MiscReg &val, ThreadContext * tc);
283 return priContext | (uint32_t)partId << 13;
288 return priContext | (uint32_t)partId << 13;
291 void serialize(std::ostream & os);
293 void unserialize(Checkpoint * cp, const std::string & section);
295 void copyMiscRegs(ThreadContext * tc);
299 bool isHyperPriv() { return (hpstate & (1 << 2)); }
300 bool isPriv() { return (hpstate & (1 << 2)) || (pstate & (1 << 2)); }
301 bool isNonPriv() { return !isPriv(); }