src/arch/sparc/miscregfile.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_MISCREGFILE_HH__
  33 #define __ARCH_SPARC_MISCREGFILE_HH__
  34
  35 #include "arch/sparc/asi.hh"
  36 #include "arch/sparc/faults.hh"
  37 #include "arch/sparc/isa_traits.hh"
  38 #include "arch/sparc/types.hh"
  39 #include "cpu/cpuevent.hh"
  40
  41 #include <string>
  42
  43 namespace SparcISA
  44 {
  45
  46     //These functions map register indices to names
  47     std::string getMiscRegName(RegIndex);
  48
  49     const int AsrStart = 0;
  50     const int PrStart = 32;
  51     const int HprStart = 64;
  52     const int MiscStart = 96;
  53
  54     enum MiscRegIndex
  55     {
  56         /** Ancillary State Registers */
  57         MISCREG_Y  = AsrStart + 0,
  58         MISCREG_CCR = AsrStart + 2,
  59         MISCREG_ASI = AsrStart + 3,
  60         MISCREG_TICK = AsrStart + 4,
  61         MISCREG_FPRS = AsrStart + 6,
  62         MISCREG_PCR = AsrStart + 16,
  63         MISCREG_PIC = AsrStart + 17,
  64         MISCREG_GSR = AsrStart + 19,
  65         MISCREG_SOFTINT_SET = AsrStart + 20,
  66         MISCREG_SOFTINT_CLR = AsrStart + 21,
  67         MISCREG_SOFTINT = AsrStart + 22,
  68         MISCREG_TICK_CMPR = AsrStart + 23,
  69         MISCREG_STICK = AsrStart + 24,
  70         MISCREG_STICK_CMPR = AsrStart + 25,
  71
  72         /** Privilged Registers */
  73         MISCREG_TPC = PrStart + 0,
  74         MISCREG_TNPC = PrStart + 1,
  75         MISCREG_TSTATE = PrStart + 2,
  76         MISCREG_TT = PrStart + 3,
  77         MISCREG_PRIVTICK = PrStart + 4,
  78         MISCREG_TBA = PrStart + 5,
  79         MISCREG_PSTATE = PrStart + 6,
  80         MISCREG_TL = PrStart + 7,
  81         MISCREG_PIL = PrStart + 8,
  82         MISCREG_CWP = PrStart + 9,
  83         MISCREG_CANSAVE = PrStart + 10,
  84         MISCREG_CANRESTORE = PrStart + 11,
  85         MISCREG_CLEANWIN = PrStart + 12,
  86         MISCREG_OTHERWIN = PrStart + 13,
  87         MISCREG_WSTATE = PrStart + 14,
  88         MISCREG_GL = PrStart + 16,
  89
  90         /** Hyper privileged registers */
  91         MISCREG_HPSTATE = HprStart + 0,
  92         MISCREG_HTSTATE = HprStart + 1,
  93         MISCREG_HINTP = HprStart + 3,
  94         MISCREG_HTBA = HprStart + 5,
  95         MISCREG_HVER = HprStart + 6,
  96         MISCREG_STRAND_STS_REG = HprStart + 16,
  97         MISCREG_HSTICK_CMPR = HprStart + 31,
  98
  99         /** Floating Point Status Register */
 100         MISCREG_FSR = MiscStart + 0
 101
 102     };
 103
 104     // The control registers, broken out into fields
 105     class MiscRegFile
 106     {
 107       private:
 108
 109         /* ASR Registers */
 110         union {
 111             uint64_t y;         // Y (used in obsolete multiplication)
 112             struct {
 113                 uint64_t value:32;      // The actual value stored in y
 114                 uint64_t :32;   // reserved bits
 115             } yFields;
 116         };
 117         union {
 118             uint8_t     ccr;            // Condition Code Register
 119             struct {
 120                 union {
 121                     uint8_t icc:4;      // 32-bit condition codes
 122                     struct {
 123                         uint8_t c:1;    // Carry
 124                         uint8_t v:1;    // Overflow
 125                         uint8_t z:1;    // Zero
 126                         uint8_t n:1;    // Negative
 127                     } iccFields;
 128                 };
 129                 union {
 130                     uint8_t xcc:4;      // 64-bit condition codes
 131                     struct {
 132                         uint8_t c:1;    // Carry
 133                         uint8_t v:1;    // Overflow
 134                         uint8_t z:1;    // Zero
 135                         uint8_t n:1;    // Negative
 136                     } xccFields;
 137                 };
 138             } ccrFields;
 139         };
 140         uint8_t asi;            // Address Space Identifier
 141         union {
 142             uint64_t tick;              // Hardware clock-tick counter
 143             struct {
 144                 int64_t counter:63;     // Clock-tick count
 145                 uint64_t npt:1;         // Non-priveleged trap
 146             } tickFields;
 147         };
 148         union {
 149             uint8_t             fprs;   // Floating-Point Register State
 150             struct {
 151                 uint8_t dl:1;           // Dirty lower
 152                 uint8_t du:1;           // Dirty upper
 153                 uint8_t fef:1;          // FPRS enable floating-Point
 154             } fprsFields;
 155         };
 156         union {
 157             uint64_t gsr;               //General Status Register
 158             struct {
 159                 uint64_t mask:32;
 160                 uint64_t :4;
 161                 uint64_t im:1;
 162                 uint64_t irnd:2;
 163                 uint64_t :17;
 164                 uint64_t scale:5;
 165                 uint64_t align:3;
 166             } gsrFields;
 167         };
 168         union {
 169             uint64_t softint;
 170             struct {
 171                 uint64_t tm:1;
 172                 uint64_t int_level:14;
 173                 uint64_t sm:1;
 174             } softintFields;
 175         };
 176         union {
 177             uint64_t tick_cmpr;         // Hardware tick compare registers
 178             struct {
 179                 uint64_t tick_cmpr:63;  // Clock-tick count
 180                 uint64_t int_dis:1;             // Non-priveleged trap
 181             } tick_cmprFields;
 182         };
 183         union {
 184             uint64_t stick;             // Hardware clock-tick counter
 185             struct {
 186                 int64_t :63;    // Not used, storage in SparcSystem
 187                 uint64_t npt:1;         // Non-priveleged trap
 188             } stickFields;
 189         };
 190         union {
 191             uint64_t stick_cmpr;                // Hardware tick compare registers
 192             struct {
 193                 uint64_t tick_cmpr:63;  // Clock-tick count
 194                 uint64_t int_dis:1;             // Non-priveleged trap
 195             } stick_cmprFields;
 196         };
 197
 198
 199         /* Privileged Registers */
 200         uint64_t tpc[MaxTL];    // Trap Program Counter (value from
 201                                 // previous trap level)
 202         uint64_t tnpc[MaxTL];   // Trap Next Program Counter (value from
 203                                 // previous trap level)
 204         union {
 205             uint64_t tstate[MaxTL];     // Trap State
 206             struct {
 207                 //Values are from previous trap level
 208                 uint64_t cwp:5;         // Current Window Pointer
 209                 uint64_t :3;    // Reserved bits
 210                 uint64_t pstate:13;     // Process State
 211                 uint64_t :3;    // Reserved bits
 212                 uint64_t asi:8;         // Address Space Identifier
 213                 uint64_t ccr:8;         // Condition Code Register
 214                 uint64_t gl:8;          // Global level
 215             } tstateFields[MaxTL];
 216         };
 217         uint16_t tt[MaxTL];     // Trap Type (Type of trap which occured
 218                                 // on the previous level)
 219         uint64_t tba;           // Trap Base Address
 220
 221         union {
 222             uint16_t pstate;            // Process State Register
 223             struct {
 224                 uint16_t :1;            // reserved
 225                 uint16_t ie:1;          // Interrupt enable
 226                 uint16_t priv:1;        // Privelege mode
 227                 uint16_t am:1;          // Address mask
 228                 uint16_t pef:1;         // PSTATE enable floating-point
 229                 uint16_t :1;            // reserved2
 230                 uint16_t mm:2;          // Memory Model
 231                 uint16_t tle:1;         // Trap little-endian
 232                 uint16_t cle:1;         // Current little-endian
 233             } pstateFields;
 234         };
 235         uint8_t tl;             // Trap Level
 236         uint8_t pil;            // Process Interrupt Register
 237         uint8_t cwp;            // Current Window Pointer
 238         uint8_t cansave;        // Savable windows
 239         uint8_t canrestore;     // Restorable windows
 240         uint8_t cleanwin;       // Clean windows
 241         uint8_t otherwin;       // Other windows
 242         union {
 243             uint8_t wstate;             // Window State
 244             struct {
 245                 uint8_t normal:3;       // Bits TT<4:2> are set to on a normal
 246                                         // register window trap
 247                 uint8_t other:3;        // Bits TT<4:2> are set to on an "otherwin"
 248                                         // register window trap
 249             } wstateFields;
 250         };
 251         uint8_t gl;             // Global level register
 252
 253
 254         /** Hyperprivileged Registers */
 255         union {
 256             uint64_t hpstate; // Hyperprivileged State Register
 257             struct {
 258                 uint8_t tlz: 1;
 259                 uint8_t :1;
 260                 uint8_t hpriv:1;
 261                 uint8_t :2;
 262                 uint8_t red:1;
 263                 uint8_t :4;
 264                 uint8_t ibe:1;
 265                 uint8_t id:1;
 266             } hpstateFields;
 267         };
 268
 269         uint64_t htstate[MaxTL]; // Hyperprivileged Trap State Register
 270         uint64_t hintp;
 271         uint64_t htba; // Hyperprivileged Trap Base Address register
 272         union {
 273             uint64_t hstick_cmpr;               // Hardware tick compare registers
 274             struct {
 275                 uint64_t tick_cmpr:63;  // Clock-tick count
 276                 uint64_t int_dis:1;             // Non-priveleged trap
 277             } hstick_cmprFields;
 278         };
 279
 280         uint64_t strandStatusReg; // Per strand status register
 281
 282
 283         /** Floating point misc registers. */
 284         union {
 285             uint64_t    fsr;    // Floating-Point State Register
 286             struct {
 287                 union {
 288                     uint64_t cexc:5;    // Current excpetion
 289                     struct {
 290                         uint64_t nxc:1;         // Inexact
 291                         uint64_t dzc:1;         // Divide by zero
 292                         uint64_t ufc:1;         // Underflow
 293                         uint64_t ofc:1;         // Overflow
 294                         uint64_t nvc:1;         // Invalid operand
 295                     } cexcFields;
 296                 };
 297                 union {
 298                     uint64_t aexc:5;            // Accrued exception
 299                     struct {
 300                         uint64_t nxc:1;         // Inexact
 301                         uint64_t dzc:1;         // Divide by zero
 302                         uint64_t ufc:1;         // Underflow
 303                         uint64_t ofc:1;         // Overflow
 304                         uint64_t nvc:1;         // Invalid operand
 305                     } aexcFields;
 306                 };
 307                 uint64_t fcc0:2;                // Floating-Point condtion codes
 308                 uint64_t :1;            // Reserved bits
 309                 uint64_t qne:1;                 // Deferred trap queue not empty
 310                                                 // with no queue, it should read 0
 311                 uint64_t ftt:3;                 // Floating-Point trap type
 312                 uint64_t ver:3;                 // Version (of the FPU)
 313                 uint64_t :2;            // Reserved bits
 314                 uint64_t ns:1;                  // Nonstandard floating point
 315                 union {
 316                     uint64_t tem:5;                     // Trap Enable Mask
 317                     struct {
 318                         uint64_t nxm:1;         // Inexact
 319                         uint64_t dzm:1;         // Divide by zero
 320                         uint64_t ufm:1;         // Underflow
 321                         uint64_t ofm:1;         // Overflow
 322                         uint64_t nvm:1;         // Invalid operand
 323                     } temFields;
 324                 };
 325                 uint64_t :2;            // Reserved bits
 326                 uint64_t rd:2;                  // Rounding direction
 327                 uint64_t fcc1:2;                // Floating-Point condition codes
 328                 uint64_t fcc2:2;                // Floating-Point condition codes
 329                 uint64_t fcc3:2;                // Floating-Point condition codes
 330                 uint64_t :26;           // Reserved bits
 331             } fsrFields;
 332         };
 333
 334         ASI implicitInstAsi;
 335         ASI implicitDataAsi;
 336
 337         // These need to check the int_dis field and if 0 then
 338         // set appropriate bit in softint and checkinterrutps on the cpu
 339 #if FULL_SYSTEM
 340         /** Process a tick compare event and generate an interrupt on the cpu if
 341          * appropriate. */
 342         void processTickCompare(ThreadContext *tc);
 343         void processSTickCompare(ThreadContext *tc);
 344         void processHSTickCompare(ThreadContext *tc);
 345
 346         typedef CpuEventWrapper<MiscRegFile,
 347                 &MiscRegFile::processTickCompare> TickCompareEvent;
 348         TickCompareEvent *tickCompare;
 349
 350         typedef CpuEventWrapper<MiscRegFile,
 351                 &MiscRegFile::processSTickCompare> STickCompareEvent;
 352         STickCompareEvent *sTickCompare;
 353
 354         typedef CpuEventWrapper<MiscRegFile,
 355                 &MiscRegFile::processHSTickCompare> HSTickCompareEvent;
 356         HSTickCompareEvent *hSTickCompare;
 357 #endif
 358       public:
 359
 360         void reset();
 361
 362         MiscRegFile()
 363         {
 364             reset();
 365         }
 366
 367         MiscReg readReg(int miscReg);
 368
 369         MiscReg readRegWithEffect(int miscReg, ThreadContext *tc);
 370
 371         void setReg(int miscReg, const MiscReg &val);
 372
 373         void setRegWithEffect(int miscReg,
 374                 const MiscReg &val, ThreadContext * tc);
 375
 376         ASI getInstAsid()
 377         {
 378             return implicitInstAsi;
 379         }
 380
 381         ASI getDataAsid()
 382         {
 383             return implicitDataAsi;
 384         }
 385
 386         void serialize(std::ostream & os);
 387
 388         void unserialize(Checkpoint * cp, const std::string & section);
 389
 390         void copyMiscRegs(ThreadContext * tc);
 391
 392       protected:
 393
 394         bool isHyperPriv() { return hpstateFields.hpriv; }
 395         bool isPriv() { return hpstateFields.hpriv || pstateFields.priv; }
 396         bool isNonPriv() { return !isPriv(); }
 397         inline void setImplicitAsis();
 398     };
 399 }
 400
 401 #endif