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32 #ifndef __ARCH_SPARC_MISCREGS_HH__
33 #define __ARCH_SPARC_MISCREGS_HH__
35 #include "base/bitunion.hh"
36 #include "base/types.hh"
42 /** Ancillary State Registers */
53 MISCREG_SOFTINT, /* 10 */
58 /** Privilged Registers */
65 MISCREG_PSTATE, /* 20 */
70 // MISCREG_CANRESTORE,
76 /** Hyper privileged registers */
77 MISCREG_HPSTATE, /* 30 */
82 MISCREG_STRAND_STS_REG,
85 /** Floating Point Status Register */
88 /** MMU Internal Registers */
89 MISCREG_MMU_P_CONTEXT,
90 MISCREG_MMU_S_CONTEXT, /* 40 */
94 /** Scratchpad regiscers **/
95 MISCREG_SCRATCHPAD_R0, /* 60 */
96 MISCREG_SCRATCHPAD_R1,
97 MISCREG_SCRATCHPAD_R2,
98 MISCREG_SCRATCHPAD_R3,
99 MISCREG_SCRATCHPAD_R4,
100 MISCREG_SCRATCHPAD_R5,
101 MISCREG_SCRATCHPAD_R6,
102 MISCREG_SCRATCHPAD_R7,
104 /* CPU Queue Registers */
105 MISCREG_QUEUE_CPU_MONDO_HEAD,
106 MISCREG_QUEUE_CPU_MONDO_TAIL,
107 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
108 MISCREG_QUEUE_DEV_MONDO_TAIL,
109 MISCREG_QUEUE_RES_ERROR_HEAD,
110 MISCREG_QUEUE_RES_ERROR_TAIL,
111 MISCREG_QUEUE_NRES_ERROR_HEAD,
112 MISCREG_QUEUE_NRES_ERROR_TAIL,
114 /* All the data for the TLB packed up in one register. */
124 Bitfield<11> id; // this impl. dependent (id) field m
141 const static int st_idle = 0x00;
142 const static int st_wait = 0x01;
143 const static int st_halt = 0x02;
144 const static int st_run = 0x05;
145 const static int st_spec_run = 0x07;
146 const static int st_spec_rdy = 0x13;
147 const static int st_ready = 0x19;
148 const static int active = 0x01;
149 const static int speculative = 0x04;
150 const static int shft_id = 8;
151 const static int shft_fsm0 = 31;
152 const static int shft_fsm1 = 26;
153 const static int shft_fsm2 = 21;
154 const static int shft_fsm3 = 16;
158 const int NumMiscRegs = MISCREG_NUMMISCREGS;