src/arch/sparc/miscregs.hh

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #ifndef __ARCH_SPARC_MISCREGS_HH__
  33 #define __ARCH_SPARC_MISCREGS_HH__
  34
  35 #include "base/bitunion.hh"
  36 #include "base/types.hh"
  37
  38 namespace SparcISA
  39 {
  40 enum MiscRegIndex
  41 {
  42     /** Ancillary State Registers */
  43 //    MISCREG_Y,
  44 //    MISCREG_CCR,
  45     MISCREG_ASI,
  46     MISCREG_TICK,
  47     MISCREG_FPRS,
  48     MISCREG_PCR,
  49     MISCREG_PIC,
  50     MISCREG_GSR,
  51     MISCREG_SOFTINT_SET,
  52     MISCREG_SOFTINT_CLR,
  53     MISCREG_SOFTINT, /* 10 */
  54     MISCREG_TICK_CMPR,
  55     MISCREG_STICK,
  56     MISCREG_STICK_CMPR,
  57
  58     /** Privilged Registers */
  59     MISCREG_TPC,
  60     MISCREG_TNPC,
  61     MISCREG_TSTATE,
  62     MISCREG_TT,
  63     MISCREG_PRIVTICK,
  64     MISCREG_TBA,
  65     MISCREG_PSTATE, /* 20 */
  66     MISCREG_TL,
  67     MISCREG_PIL,
  68     MISCREG_CWP,
  69 //    MISCREG_CANSAVE,
  70 //    MISCREG_CANRESTORE,
  71 //    MISCREG_CLEANWIN,
  72 //    MISCREG_OTHERWIN,
  73 //    MISCREG_WSTATE,
  74     MISCREG_GL,
  75
  76     /** Hyper privileged registers */
  77     MISCREG_HPSTATE, /* 30 */
  78     MISCREG_HTSTATE,
  79     MISCREG_HINTP,
  80     MISCREG_HTBA,
  81     MISCREG_HVER,
  82     MISCREG_STRAND_STS_REG,
  83     MISCREG_HSTICK_CMPR,
  84
  85     /** Floating Point Status Register */
  86     MISCREG_FSR,
  87
  88     /** MMU Internal Registers */
  89     MISCREG_MMU_P_CONTEXT,
  90     MISCREG_MMU_S_CONTEXT, /* 40 */
  91     MISCREG_MMU_PART_ID,
  92     MISCREG_MMU_LSU_CTRL,
  93
  94     /** Scratchpad regiscers **/
  95     MISCREG_SCRATCHPAD_R0, /* 60 */
  96     MISCREG_SCRATCHPAD_R1,
  97     MISCREG_SCRATCHPAD_R2,
  98     MISCREG_SCRATCHPAD_R3,
  99     MISCREG_SCRATCHPAD_R4,
 100     MISCREG_SCRATCHPAD_R5,
 101     MISCREG_SCRATCHPAD_R6,
 102     MISCREG_SCRATCHPAD_R7,
 103
 104     /* CPU Queue Registers */
 105     MISCREG_QUEUE_CPU_MONDO_HEAD,
 106     MISCREG_QUEUE_CPU_MONDO_TAIL,
 107     MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
 108     MISCREG_QUEUE_DEV_MONDO_TAIL,
 109     MISCREG_QUEUE_RES_ERROR_HEAD,
 110     MISCREG_QUEUE_RES_ERROR_TAIL,
 111     MISCREG_QUEUE_NRES_ERROR_HEAD,
 112     MISCREG_QUEUE_NRES_ERROR_TAIL,
 113
 114     /* All the data for the TLB packed up in one register. */
 115     MISCREG_TLB_DATA,
 116     MISCREG_NUMMISCREGS
 117 };
 118
 119 BitUnion64(HPSTATE)
 120     Bitfield<0> tlz;
 121     Bitfield<2> hpriv;
 122     Bitfield<5> red;
 123     Bitfield<10> ibe;
 124     Bitfield<11> id;  // this impl. dependent (id) field m
 125 EndBitUnion(HPSTATE)
 126
 127 BitUnion16(PSTATE)
 128     Bitfield<1> ie;
 129     Bitfield<2> priv;
 130     Bitfield<3> am;
 131     Bitfield<4> pef;
 132     Bitfield<7, 6> mm;
 133     Bitfield<8> tle;
 134     Bitfield<9> cle;
 135     Bitfield<10> pid0;
 136     Bitfield<11> pid1;
 137 EndBitUnion(PSTATE)
 138
 139 struct STS
 140 {
 141     const static int st_idle     = 0x00;
 142     const static int st_wait     = 0x01;
 143     const static int st_halt     = 0x02;
 144     const static int st_run      = 0x05;
 145     const static int st_spec_run = 0x07;
 146     const static int st_spec_rdy = 0x13;
 147     const static int st_ready    = 0x19;
 148     const static int active      = 0x01;
 149     const static int speculative = 0x04;
 150     const static int shft_id     = 8;
 151     const static int shft_fsm0   = 31;
 152     const static int shft_fsm1   = 26;
 153     const static int shft_fsm2   = 21;
 154     const static int shft_fsm3   = 16;
 155 };
 156
 157
 158 const int NumMiscRegs = MISCREG_NUMMISCREGS;
 159
 160 }
 161
 162 #endif