2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #ifndef __ARCH_SPARC_MISCREGS_HH__
33 #define __ARCH_SPARC_MISCREGS_HH__
35 #include "base/types.hh"
41 /** Ancillary State Registers */
52 MISCREG_SOFTINT, /* 10 */
57 /** Privilged Registers */
64 MISCREG_PSTATE, /* 20 */
69 // MISCREG_CANRESTORE,
75 /** Hyper privileged registers */
76 MISCREG_HPSTATE, /* 30 */
81 MISCREG_STRAND_STS_REG,
84 /** Floating Point Status Register */
87 /** MMU Internal Registers */
88 MISCREG_MMU_P_CONTEXT,
89 MISCREG_MMU_S_CONTEXT, /* 40 */
93 /** Scratchpad regiscers **/
94 MISCREG_SCRATCHPAD_R0, /* 60 */
95 MISCREG_SCRATCHPAD_R1,
96 MISCREG_SCRATCHPAD_R2,
97 MISCREG_SCRATCHPAD_R3,
98 MISCREG_SCRATCHPAD_R4,
99 MISCREG_SCRATCHPAD_R5,
100 MISCREG_SCRATCHPAD_R6,
101 MISCREG_SCRATCHPAD_R7,
103 /* CPU Queue Registers */
104 MISCREG_QUEUE_CPU_MONDO_HEAD,
105 MISCREG_QUEUE_CPU_MONDO_TAIL,
106 MISCREG_QUEUE_DEV_MONDO_HEAD, /* 70 */
107 MISCREG_QUEUE_DEV_MONDO_TAIL,
108 MISCREG_QUEUE_RES_ERROR_HEAD,
109 MISCREG_QUEUE_RES_ERROR_TAIL,
110 MISCREG_QUEUE_NRES_ERROR_HEAD,
111 MISCREG_QUEUE_NRES_ERROR_TAIL,
113 /* All the data for the TLB packed up in one register. */
119 const static uint64_t id = 0x800; // this impl. dependent (id) field m
120 const static uint64_t ibe = 0x400;
121 const static uint64_t red = 0x20;
122 const static uint64_t hpriv = 0x4;
123 const static uint64_t tlz = 0x1;
128 const static int cle = 0x200;
129 const static int tle = 0x100;
130 const static int mm = 0xC0;
131 const static int pef = 0x10;
132 const static int am = 0x8;
133 const static int priv = 0x4;
134 const static int ie = 0x2;
138 const static int st_idle = 0x00;
139 const static int st_wait = 0x01;
140 const static int st_halt = 0x02;
141 const static int st_run = 0x05;
142 const static int st_spec_run = 0x07;
143 const static int st_spec_rdy = 0x13;
144 const static int st_ready = 0x19;
145 const static int active = 0x01;
146 const static int speculative = 0x04;
147 const static int shft_id = 8;
148 const static int shft_fsm0 = 31;
149 const static int shft_fsm1 = 26;
150 const static int shft_fsm2 = 21;
151 const static int shft_fsm3 = 16;
155 const int NumMiscArchRegs = MISCREG_NUMMISCREGS;
156 const int NumMiscRegs = MISCREG_NUMMISCREGS;