Merge with head.
[gem5.git] / src / arch / sparc / nativetrace.cc
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #include "arch/sparc/isa_traits.hh"
32 #include "arch/sparc/registers.hh"
33 #include "arch/sparc/nativetrace.hh"
34 #include "cpu/thread_context.hh"
35 #include "params/SparcNativeTrace.hh"
36
37 namespace Trace {
38
39 static const char *intRegNames[SparcISA::NumIntArchRegs] = {
40 //Global registers
41 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
42 //Output registers
43 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
44 //Local registers
45 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
46 //Input registers
47 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
48 };
49
50 void
51 Trace::SparcNativeTrace::check(NativeTraceRecord *record)
52 {
53 ThreadContext *tc = record->getThread();
54
55 uint64_t regVal, realRegVal;
56
57 // Integer registers
58
59 // I doubt a real SPARC will describe more integer registers than this.
60 assert(SparcISA::NumIntArchRegs == 32);
61 const char **regName = intRegNames;
62 for (int i = 0; i < SparcISA::NumIntArchRegs; i++) {
63 regVal = tc->readIntReg(i);
64 read(&realRegVal, sizeof(realRegVal));
65 realRegVal = SparcISA::gtoh(realRegVal);
66 checkReg(*(regName++), regVal, realRegVal);
67 }
68
69 // PC
70 read(&realRegVal, sizeof(realRegVal));
71 realRegVal = SparcISA::gtoh(realRegVal);
72 regVal = tc->readNextPC();
73 checkReg("pc", regVal, realRegVal);
74
75 // NPC
76 read(&realRegVal, sizeof(realRegVal));
77 realRegVal = SparcISA::gtoh(realRegVal);
78 regVal = tc->readNextNPC();
79 checkReg("npc", regVal, realRegVal);
80
81 // CCR
82 read(&realRegVal, sizeof(realRegVal));
83 realRegVal = SparcISA::gtoh(realRegVal);
84 regVal = tc->readIntReg(SparcISA::NumIntArchRegs + 2);
85 checkReg("ccr", regVal, realRegVal);
86 }
87
88 } /* namespace Trace */
89
90 ////////////////////////////////////////////////////////////////////////
91 //
92 // ExeTracer Simulation Object
93 //
94 Trace::SparcNativeTrace *
95 SparcNativeTraceParams::create()
96 {
97 return new Trace::SparcNativeTrace(this);
98 };