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31 #include "arch/sparc/isa_traits.hh"
32 #include "arch/sparc/registers.hh"
33 #include "arch/sparc/nativetrace.hh"
34 #include "cpu/thread_context.hh"
35 #include "params/SparcNativeTrace.hh"
39 static const char *intRegNames
[SparcISA::NumIntArchRegs
] = {
41 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
43 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
45 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
47 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
51 Trace::SparcNativeTrace::check(NativeTraceRecord
*record
)
53 ThreadContext
*tc
= record
->getThread();
55 uint64_t regVal
, realRegVal
;
59 // I doubt a real SPARC will describe more integer registers than this.
60 assert(SparcISA::NumIntArchRegs
== 32);
61 const char **regName
= intRegNames
;
62 for (int i
= 0; i
< SparcISA::NumIntArchRegs
; i
++) {
63 regVal
= tc
->readIntReg(i
);
64 read(&realRegVal
, sizeof(realRegVal
));
65 realRegVal
= SparcISA::gtoh(realRegVal
);
66 checkReg(*(regName
++), regVal
, realRegVal
);
70 read(&realRegVal
, sizeof(realRegVal
));
71 realRegVal
= SparcISA::gtoh(realRegVal
);
72 regVal
= tc
->readNextPC();
73 checkReg("pc", regVal
, realRegVal
);
76 read(&realRegVal
, sizeof(realRegVal
));
77 realRegVal
= SparcISA::gtoh(realRegVal
);
78 regVal
= tc
->readNextNPC();
79 checkReg("npc", regVal
, realRegVal
);
82 read(&realRegVal
, sizeof(realRegVal
));
83 realRegVal
= SparcISA::gtoh(realRegVal
);
84 regVal
= tc
->readIntReg(SparcISA::NumIntArchRegs
+ 2);
85 checkReg("ccr", regVal
, realRegVal
);
88 } /* namespace Trace */
90 ////////////////////////////////////////////////////////////////////////
92 // ExeTracer Simulation Object
94 Trace::SparcNativeTrace
*
95 SparcNativeTraceParams::create()
97 return new Trace::SparcNativeTrace(this);