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31 #include "arch/sparc/isa_traits.hh"
32 #include "arch/sparc/nativetrace.hh"
33 #include "arch/sparc/registers.hh"
34 #include "cpu/thread_context.hh"
35 #include "params/SparcNativeTrace.hh"
36 #include "sim/byteswap.hh"
40 static const char *intRegNames
[SparcISA::NumIntArchRegs
] = {
42 "g0", "g1", "g2", "g3", "g4", "g5", "g6", "g7",
44 "o0", "o1", "o2", "o3", "o4", "o5", "o6", "o7",
46 "l0", "l1", "l2", "l3", "l4", "l5", "l6", "l7",
48 "i0", "i1", "i2", "i3", "i4", "i5", "i6", "i7",
52 Trace::SparcNativeTrace::check(NativeTraceRecord
*record
)
54 ThreadContext
*tc
= record
->getThread();
56 uint64_t regVal
, realRegVal
;
60 // I doubt a real SPARC will describe more integer registers than this.
61 assert(SparcISA::NumIntArchRegs
== 32);
62 const char **regName
= intRegNames
;
63 for (int i
= 0; i
< SparcISA::NumIntArchRegs
; i
++) {
64 regVal
= tc
->readIntReg(i
);
65 read(&realRegVal
, sizeof(realRegVal
));
66 realRegVal
= SparcISA::gtoh(realRegVal
);
67 checkReg(*(regName
++), regVal
, realRegVal
);
70 SparcISA::PCState pc
= tc
->pcState();
72 read(&realRegVal
, sizeof(realRegVal
));
73 realRegVal
= SparcISA::gtoh(realRegVal
);
75 checkReg("pc", regVal
, realRegVal
);
78 read(&realRegVal
, sizeof(realRegVal
));
79 realRegVal
= SparcISA::gtoh(realRegVal
);
81 checkReg("npc", regVal
, realRegVal
);
84 read(&realRegVal
, sizeof(realRegVal
));
85 realRegVal
= SparcISA::gtoh(realRegVal
);
86 regVal
= tc
->readIntReg(SparcISA::NumIntArchRegs
+ 2);
87 checkReg("ccr", regVal
, realRegVal
);
92 ////////////////////////////////////////////////////////////////////////
94 // ExeTracer Simulation Object
96 Trace::SparcNativeTrace
*
97 SparcNativeTraceParams::create()
99 return new Trace::SparcNativeTrace(this);