src/arch/sparc/pagetable.hh

   1 /*
   2  * Copyright (c) 2006 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  */
  28
  29 #ifndef __ARCH_SPARC_PAGETABLE_HH__
  30 #define __ARCH_SPARC_PAGETABLE_HH__
  31
  32 #include <cassert>
  33
  34 #include "arch/sparc/isa_traits.hh"
  35 #include "base/bitfield.hh"
  36 #include "base/logging.hh"
  37
  38 class Checkpoint;
  39
  40 namespace SparcISA
  41 {
  42
  43 class TteTag
  44 {
  45   private:
  46     uint64_t entry;
  47     bool populated;
  48
  49   public:
  50     TteTag() : entry(0), populated(false) {}
  51     TteTag(uint64_t e) : entry(e), populated(true) {}
  52
  53     const TteTag &
  54     operator=(uint64_t e)
  55     {
  56         populated = true;
  57         entry = e;
  58         return *this;
  59     }
  60
  61     bool valid() const { assert(populated); return !bits(entry,62,62); }
  62     Addr va()    const { assert(populated); return bits(entry,41,0); }
  63 };
  64
  65
  66 class PageTableEntry
  67 {
  68   public:
  69     enum EntryType {
  70       sun4v,
  71       sun4u,
  72       invalid
  73     };
  74
  75   private:
  76     uint64_t entry;
  77     EntryType type;
  78     uint64_t entry4u;
  79     bool populated;
  80
  81   public:
  82     PageTableEntry() : entry(0), type(invalid), populated(false)
  83     {}
  84
  85     PageTableEntry(uint64_t e, EntryType t = sun4u)
  86         : entry(e), type(t), populated(true)
  87     {
  88         populate(entry, type);
  89     }
  90
  91     void
  92     populate(uint64_t e, EntryType t = sun4u)
  93     {
  94         entry = e;
  95         type = t;
  96         populated = true;
  97
  98         // If we get a sun4v format TTE, turn it into a sun4u
  99         if (type == sun4u)
 100             entry4u = entry;
 101         else {
 102             entry4u = 0;
 103             entry4u |= mbits(entry,63,63);         // valid
 104             entry4u |= bits(entry,1,0) << 61;      // size[1:0]
 105             entry4u |= bits(entry,62,62) << 60;    // nfo
 106             entry4u |= bits(entry,12,12) << 59;    // ie
 107             entry4u |= bits(entry,2,2) << 48;      // size[2]
 108             entry4u |= mbits(entry,39,13);         // paddr
 109             entry4u |= bits(entry,61,61) << 6;;    // locked
 110             entry4u |= bits(entry,10,10) << 5;     // cp
 111             entry4u |= bits(entry,9,9) << 4;       // cv
 112             entry4u |= bits(entry,11,11) << 3;     // e
 113             entry4u |= bits(entry,8,8) << 2;       // p
 114             entry4u |= bits(entry,6,6) << 1;       // w
 115         }
 116     }
 117
 118     void
 119     clear()
 120     {
 121         populated = false;
 122     }
 123
 124     static int pageSizes[6];
 125
 126     uint64_t operator()() const { assert(populated); return entry4u; }
 127
 128     const PageTableEntry &
 129     operator=(uint64_t e)
 130     {
 131         populated = true;
 132         entry4u = e;
 133         return *this;
 134     }
 135
 136     const PageTableEntry &
 137     operator=(const PageTableEntry &e)
 138     {
 139         populated = true;
 140         entry4u = e.entry4u;
 141         type = e.type;
 142         return *this;
 143     }
 144
 145     bool valid() const { return bits(entry4u,63,63) && populated; }
 146
 147     uint8_t
 148     _size() const
 149     {
 150         assert(populated);
 151         return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
 152     }
 153
 154     Addr size()     const { assert(_size() < 6); return pageSizes[_size()]; }
 155     Addr sizeMask() const { return size() - 1; }
 156     bool ie()       const { return bits(entry4u, 59,59); }
 157     Addr pfn()      const { assert(populated); return bits(entry4u,39,13); }
 158     Addr paddr()    const { assert(populated); return mbits(entry4u, 39,13);}
 159     bool locked()   const { assert(populated); return bits(entry4u,6,6); }
 160     bool cv()       const { assert(populated); return bits(entry4u,4,4); }
 161     bool cp()       const { assert(populated); return bits(entry4u,5,5); }
 162     bool priv()     const { assert(populated); return bits(entry4u,2,2); }
 163     bool writable() const { assert(populated); return bits(entry4u,1,1); }
 164     bool nofault()  const { assert(populated); return bits(entry4u,60,60); }
 165     bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
 166     Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
 167
 168     Addr
 169     translate(Addr vaddr) const
 170     {
 171         assert(populated);
 172         Addr mask = sizeMask();
 173         return (paddr() & ~mask) | (vaddr & mask);
 174     }
 175 };
 176
 177 struct TlbRange
 178 {
 179     Addr va;
 180     Addr size;
 181     int contextId;
 182     int partitionId;
 183     bool real;
 184
 185     inline bool
 186     operator<(const TlbRange &r2) const
 187     {
 188         if (real && !r2.real)
 189             return true;
 190         if (!real && r2.real)
 191             return false;
 192
 193         if (!real && !r2.real) {
 194             if (contextId < r2.contextId)
 195                 return true;
 196             else if (contextId > r2.contextId)
 197                 return false;
 198         }
 199
 200         if (partitionId < r2.partitionId)
 201             return true;
 202         else if (partitionId > r2.partitionId)
 203             return false;
 204
 205         if (va < r2.va)
 206             return true;
 207         return false;
 208     }
 209
 210     inline bool
 211     operator==(const TlbRange &r2) const
 212     {
 213         return va == r2.va &&
 214                size == r2.size &&
 215                contextId == r2.contextId &&
 216                partitionId == r2.partitionId &&
 217                real == r2.real;
 218     }
 219 };
 220
 221
 222 struct TlbEntry
 223 {
 224     TlbEntry()
 225     {}
 226
 227     TlbEntry(Addr asn, Addr vaddr, Addr paddr,
 228              bool uncacheable, bool read_only)
 229     {
 230         uint64_t entry = 0;
 231         if (!read_only)
 232             entry |= 1ULL << 1; // Writable
 233         entry |= 0ULL << 2; // Available in nonpriveleged mode
 234         entry |= 0ULL << 3; // No side effects
 235         if (!uncacheable) {
 236             entry |= 1ULL << 4; // Virtually cachable
 237             entry |= 1ULL << 5; // Physically cachable
 238         }
 239         entry |= 0ULL << 6; // Not locked
 240         entry |= mbits(paddr, 39, 13); // Physical address
 241         entry |= 0ULL << 48; // size = 8k
 242         entry |= 0uLL << 59; // Endianness not inverted
 243         entry |= 0ULL << 60; // Not no fault only
 244         entry |= 0ULL << 61; // size = 8k
 245         entry |= 1ULL << 63; // valid
 246         pte = PageTableEntry(entry);
 247
 248         range.va = vaddr;
 249         range.size = 8*(1<<10);
 250         range.contextId = asn;
 251         range.partitionId = 0;
 252         range.real = false;
 253
 254         valid = true;
 255     }
 256
 257     TlbRange range;
 258     PageTableEntry pte;
 259     bool used;
 260     bool valid;
 261
 262     Addr
 263     pageStart()
 264     {
 265         return pte.paddr();
 266     }
 267
 268     void
 269     updateVaddr(Addr new_vaddr)
 270     {
 271         range.va = new_vaddr;
 272     }
 273
 274     void serialize(CheckpointOut &cp) const;
 275     void unserialize(CheckpointIn &cp);
 276 };
 277
 278 } // namespace SparcISA
 279
 280 #endif // __ARCH_SPARC_PAGE_TABLE_HH__
 281