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31 #ifndef __ARCH_SPARC_PAGETABLE_HH__
32 #define __ARCH_SPARC_PAGETABLE_HH__
36 #include "arch/sparc/isa_traits.hh"
37 #include "base/bitfield.hh"
38 #include "base/misc.hh"
46 VAddr(Addr a) { panic("not implemented yet."); }
56 TteTag() : entry(0), populated(false) {}
57 TteTag(uint64_t e) : entry(e), populated(true) {}
67 bool valid() const { assert(populated); return !bits(entry,62,62); }
68 Addr va() const { assert(populated); return bits(entry,41,0); }
88 PageTableEntry() : entry(0), type(invalid), populated(false)
91 PageTableEntry(uint64_t e, EntryType t = sun4u)
92 : entry(e), type(t), populated(true)
94 populate(entry, type);
98 populate(uint64_t e, EntryType t = sun4u)
104 // If we get a sun4v format TTE, turn it into a sun4u
109 entry4u |= mbits(entry,63,63); // valid
110 entry4u |= bits(entry,1,0) << 61; // size[1:0]
111 entry4u |= bits(entry,62,62) << 60; // nfo
112 entry4u |= bits(entry,12,12) << 59; // ie
113 entry4u |= bits(entry,2,2) << 48; // size[2]
114 entry4u |= mbits(entry,39,13); // paddr
115 entry4u |= bits(entry,61,61) << 6;; // locked
116 entry4u |= bits(entry,10,10) << 5; // cp
117 entry4u |= bits(entry,9,9) << 4; // cv
118 entry4u |= bits(entry,11,11) << 3; // e
119 entry4u |= bits(entry,8,8) << 2; // p
120 entry4u |= bits(entry,6,6) << 1; // w
130 static int pageSizes[6];
132 uint64_t operator()() const { assert(populated); return entry4u; }
134 const PageTableEntry &
135 operator=(uint64_t e)
142 const PageTableEntry &
143 operator=(const PageTableEntry &e)
151 bool valid() const { return bits(entry4u,63,63) && populated; }
157 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
160 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
161 Addr sizeMask() const { return size() - 1; }
162 bool ie() const { return bits(entry4u, 59,59); }
163 Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
164 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
165 bool locked() const { assert(populated); return bits(entry4u,6,6); }
166 bool cv() const { assert(populated); return bits(entry4u,4,4); }
167 bool cp() const { assert(populated); return bits(entry4u,5,5); }
168 bool priv() const { assert(populated); return bits(entry4u,2,2); }
169 bool writable() const { assert(populated); return bits(entry4u,1,1); }
170 bool nofault() const { assert(populated); return bits(entry4u,60,60); }
171 bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
172 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
175 translate(Addr vaddr) const
178 Addr mask = sizeMask();
179 return (paddr() & ~mask) | (vaddr & mask);
192 operator<(const TlbRange &r2) const
194 if (real && !r2.real)
196 if (!real && r2.real)
199 if (!real && !r2.real) {
200 if (contextId < r2.contextId)
202 else if (contextId > r2.contextId)
206 if (partitionId < r2.partitionId)
208 else if (partitionId > r2.partitionId)
217 operator==(const TlbRange &r2) const
219 return va == r2.va &&
221 contextId == r2.contextId &&
222 partitionId == r2.partitionId &&
233 TlbEntry(Addr asn, Addr vaddr, Addr paddr)
236 entry |= 1ULL << 1; // Writable
237 entry |= 0ULL << 2; // Available in nonpriveleged mode
238 entry |= 0ULL << 3; // No side effects
239 entry |= 1ULL << 4; // Virtually cachable
240 entry |= 1ULL << 5; // Physically cachable
241 entry |= 0ULL << 6; // Not locked
242 entry |= mbits(paddr, 39, 13); // Physical address
243 entry |= 0ULL << 48; // size = 8k
244 entry |= 0uLL << 59; // Endianness not inverted
245 entry |= 0ULL << 60; // Not no fault only
246 entry |= 0ULL << 61; // size = 8k
247 entry |= 1ULL << 63; // valid
248 pte = PageTableEntry(entry);
251 range.size = 8*(1<<10);
252 range.contextId = asn;
253 range.partitionId = 0;
271 updateVaddr(Addr new_vaddr)
273 range.va = new_vaddr;
276 void serialize(std::ostream &os);
277 void unserialize(Checkpoint *cp, const std::string §ion);
280 } // namespace SparcISA
282 #endif // __ARCH_SPARC_PAGE_TABLE_HH__