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31 #ifndef __ARCH_SPARC_PAGETABLE_HH__
32 #define __ARCH_SPARC_PAGETABLE_HH__
34 #include "arch/sparc/isa_traits.hh"
35 #include "base/bitfield.hh"
36 #include "base/misc.hh"
37 #include "config/full_system.hh"
45 VAddr(Addr a) { panic("not implemented yet."); }
55 TteTag() : entry(0), populated(false) {}
56 TteTag(uint64_t e) : entry(e), populated(true) {}
66 bool valid() const {assert(populated); return !bits(entry,62,62); }
67 Addr va() const {assert(populated); return bits(entry,41,0); }
88 : entry(0), type(invalid), populated(false)
91 PageTableEntry(uint64_t e, EntryType t = sun4u)
92 : entry(e), type(t), populated(true)
94 populate(entry, type);
97 void populate(uint64_t e, EntryType t = sun4u)
103 // If we get a sun4v format TTE, turn it into a sun4u
108 entry4u |= mbits(entry,63,63); //valid
109 entry4u |= bits(entry,1,0) << 61; //size[1:0]
110 entry4u |= bits(entry,62,62) << 60; //nfo
111 entry4u |= bits(entry,12,12) << 59; //ie
112 entry4u |= bits(entry,2,2) << 48; //size[2]
113 entry4u |= mbits(entry,39,13); //paddr
114 entry4u |= bits(entry,61,61) << 6;; // locked
115 entry4u |= bits(entry,10,10) << 5; //cp
116 entry4u |= bits(entry,9,9) << 4; //cv
117 entry4u |= bits(entry,11,11) << 3; //e
118 entry4u |= bits(entry,8,8) << 2; //p
119 entry4u |= bits(entry,6,6) << 1; //w
129 static int pageSizes[6];
131 uint64_t operator()() const { assert(populated); return entry4u; }
132 const PageTableEntry &
133 operator=(uint64_t e)
140 const PageTableEntry &
141 operator=(const PageTableEntry &e)
149 bool valid() const { return bits(entry4u,63,63) && populated; }
155 return bits(entry4u, 62,61) | bits(entry4u, 48,48) << 2;
158 Addr size() const { assert(_size() < 6); return pageSizes[_size()]; }
159 Addr sizeMask() const { return size() - 1; }
160 bool ie() const { return bits(entry4u, 59,59); }
161 Addr pfn() const { assert(populated); return bits(entry4u,39,13); }
162 Addr paddr() const { assert(populated); return mbits(entry4u, 39,13);}
163 bool locked() const { assert(populated); return bits(entry4u,6,6); }
164 bool cv() const { assert(populated); return bits(entry4u,4,4); }
165 bool cp() const { assert(populated); return bits(entry4u,5,5); }
166 bool priv() const { assert(populated); return bits(entry4u,2,2); }
167 bool writable() const { assert(populated); return bits(entry4u,1,1); }
168 bool nofault() const { assert(populated); return bits(entry4u,60,60); }
169 bool sideffect() const { assert(populated); return bits(entry4u,3,3); }
170 Addr paddrMask() const { assert(populated); return paddr() & ~sizeMask(); }
173 translate(Addr vaddr) const
176 Addr mask = sizeMask();
177 return (paddr() & ~mask) | (vaddr & mask);
190 operator<(const TlbRange &r2) const
192 if (real && !r2.real)
194 if (!real && r2.real)
197 if (!real && !r2.real) {
198 if (contextId < r2.contextId)
200 else if (contextId > r2.contextId)
204 if (partitionId < r2.partitionId)
206 else if (partitionId > r2.partitionId)
215 operator==(const TlbRange &r2) const
217 return va == r2.va &&
219 contextId == r2.contextId &&
220 partitionId == r2.partitionId &&
231 TlbEntry(Addr asn, Addr vaddr, Addr paddr)
234 entry |= 1ULL << 1; // Writable
235 entry |= 0ULL << 2; // Available in nonpriveleged mode
236 entry |= 0ULL << 3; // No side effects
237 entry |= 1ULL << 4; // Virtually cachable
238 entry |= 1ULL << 5; // Physically cachable
239 entry |= 0ULL << 6; // Not locked
240 entry |= mbits(paddr, 39, 13); // Physical address
241 entry |= 0ULL << 48; // size = 8k
242 entry |= 0uLL << 59; // Endianness not inverted
243 entry |= 0ULL << 60; // Not no fault only
244 entry |= 0ULL << 61; // size = 8k
245 entry |= 1ULL << 63; // valid
246 pte = PageTableEntry(entry);
249 range.size = 8*(1<<10);
250 range.contextId = asn;
251 range.partitionId = 0;
267 void serialize(std::ostream &os);
268 void unserialize(Checkpoint *cp, const std::string §ion);
271 } // namespace SparcISA
273 #endif // __ARCH_SPARC_PAGE_TABLE_HH__