SE: move page allocation from PageTable to Process
[gem5.git] / src / arch / sparc / predecoder.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __ARCH_SPARC_PREDECODER_HH__
32 #define __ARCH_SPARC_PREDECODER_HH__
33
34 #include "arch/sparc/registers.hh"
35 #include "arch/sparc/types.hh"
36 #include "base/bitfield.hh"
37 #include "base/misc.hh"
38 #include "base/types.hh"
39 #include "cpu/thread_context.hh"
40
41 class ThreadContext;
42
43 namespace SparcISA
44 {
45
46 class Predecoder
47 {
48 protected:
49 ThreadContext * tc;
50 // The extended machine instruction being generated
51 ExtMachInst emi;
52 bool emiIsReady;
53
54 public:
55 Predecoder(ThreadContext * _tc) : tc(_tc), emiIsReady(false)
56 {}
57
58 ThreadContext *
59 getTC()
60 {
61 return tc;
62 }
63
64 void
65 setTC(ThreadContext * _tc)
66 {
67 tc = _tc;
68 }
69
70 void process() {}
71
72 void
73 reset()
74 {
75 emiIsReady = false;
76 }
77
78 // Use this to give data to the predecoder. This should be used
79 // when there is control flow.
80 void
81 moreBytes(const PCState &pc, Addr fetchPC, MachInst inst)
82 {
83 emi = inst;
84 // The I bit, bit 13, is used to figure out where the ASI
85 // should come from. Use that in the ExtMachInst. This is
86 // slightly redundant, but it removes the need to put a condition
87 // into all the execute functions
88 if (inst & (1 << 13)) {
89 emi |= (static_cast<ExtMachInst>(
90 tc->readMiscRegNoEffect(MISCREG_ASI))
91 << (sizeof(MachInst) * 8));
92 } else {
93 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
94 << (sizeof(MachInst) * 8));
95 }
96 emiIsReady = true;
97 }
98
99 bool
100 needMoreBytes()
101 {
102 return true;
103 }
104
105 bool
106 extMachInstReady()
107 {
108 return emiIsReady;
109 }
110
111 // This returns a constant reference to the ExtMachInst to avoid a copy
112 const ExtMachInst &
113 getExtMachInst(PCState &pcState)
114 {
115 emiIsReady = false;
116 return emi;
117 }
118 };
119 };
120
121 #endif // __ARCH_SPARC_PREDECODER_HH__