Merge zizzer.eecs.umich.edu:/bk/newmem
[gem5.git] / src / arch / sparc / predecoder.hh
1 /*
2 * Copyright (c) 2006 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 */
30
31 #ifndef __ARCH_SPARC_PREDECODER_HH__
32 #define __ARCH_SPARC_PREDECODER_HH__
33
34 #include "arch/sparc/types.hh"
35 #include "base/misc.hh"
36 #include "cpu/thread_context.hh"
37 #include "sim/host.hh"
38
39 class ThreadContext;
40
41 namespace SparcISA
42 {
43 class Predecoder
44 {
45 protected:
46 ThreadContext * tc;
47 //The extended machine instruction being generated
48 ExtMachInst emi;
49
50 public:
51 Predecoder(ThreadContext * _tc) : tc(_tc)
52 {}
53
54 ThreadContext * getTC()
55 {
56 return tc;
57 }
58
59 void setTC(ThreadContext * _tc)
60 {
61 tc = _tc;
62 }
63
64 void process()
65 {
66 }
67
68 //Use this to give data to the predecoder. This should be used
69 //when there is control flow.
70 void moreBytes(Addr currPC, Addr off, MachInst inst)
71 {
72 assert(off == 0);
73
74 emi = inst;
75 //The I bit, bit 13, is used to figure out where the ASI
76 //should come from. Use that in the ExtMachInst. This is
77 //slightly redundant, but it removes the need to put a condition
78 //into all the execute functions
79 if(inst & (1 << 13))
80 emi |= (static_cast<ExtMachInst>(
81 tc->readMiscRegNoEffect(MISCREG_ASI))
82 << (sizeof(MachInst) * 8));
83 else
84 emi |= (static_cast<ExtMachInst>(bits(inst, 12, 5))
85 << (sizeof(MachInst) * 8));
86 }
87
88 //Use this to give data to the predecoder. This should be used
89 //when instructions are executed in order.
90 void moreBytes(MachInst machInst)
91 {
92 moreBytes(0, 0, machInst);
93 }
94
95 bool needMoreBytes()
96 {
97 return true;
98 }
99
100 bool extMachInstReady()
101 {
102 return true;
103 }
104
105 //This returns a constant reference to the ExtMachInst to avoid a copy
106 const ExtMachInst & getExtMachInst()
107 {
108 return emi;
109 }
110 };
111 };
112
113 #endif // __ARCH_SPARC_PREDECODER_HH__