2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "arch/sparc/asi.hh"
33 #include "arch/sparc/handlers.hh"
34 #include "arch/sparc/isa_traits.hh"
35 #include "arch/sparc/process.hh"
36 #include "arch/sparc/registers.hh"
37 #include "arch/sparc/types.hh"
38 #include "base/loader/elf_object.hh"
39 #include "base/loader/object_file.hh"
40 #include "base/misc.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/Stack.hh"
43 #include "mem/page_table.hh"
44 #include "sim/process_impl.hh"
45 #include "sim/system.hh"
48 using namespace SparcISA
;
50 static const int FirstArgumentReg
= 8;
53 SparcLiveProcess::SparcLiveProcess(LiveProcessParams
* params
,
54 ObjectFile
*objFile
, Addr _StackBias
)
55 : LiveProcess(params
, objFile
), StackBias(_StackBias
)
58 // XXX all the below need to be updated for SPARC - Ali
59 brk_point
= objFile
->dataBase() + objFile
->dataSize() + objFile
->bssSize();
60 brk_point
= roundUp(brk_point
, PageBytes
);
62 // Set pointer for next thread stack. Reserve 8M for main stack.
63 next_thread_stack_base
= stack_base
- (8 * 1024 * 1024);
65 // Initialize these to 0s
71 SparcLiveProcess::handleTrap(int trapNum
, ThreadContext
*tc
)
73 PCState pc
= tc
->pcState();
75 case 0x01: // Software breakpoint
76 warn("Software breakpoint encountered at pc %#x.\n", pc
.pc());
78 case 0x02: // Division by zero
79 warn("Software signaled a division by zero at pc %#x.\n", pc
.pc());
81 case 0x03: // Flush window trap
84 case 0x04: // Clean windows
85 warn("Ignoring process request for clean register "
86 "windows at pc %#x.\n", pc
.pc());
88 case 0x05: // Range check
89 warn("Software signaled a range check at pc %#x.\n", pc
.pc());
91 case 0x06: // Fix alignment
92 warn("Ignoring process request for os assisted unaligned accesses "
93 "at pc %#x.\n", pc
.pc());
95 case 0x07: // Integer overflow
96 warn("Software signaled an integer overflow at pc %#x.\n", pc
.pc());
98 case 0x32: // Get integer condition codes
99 warn("Ignoring process request to get the integer condition codes "
100 "at pc %#x.\n", pc
.pc());
102 case 0x33: // Set integer condition codes
103 warn("Ignoring process request to set the integer condition codes "
104 "at pc %#x.\n", pc
.pc());
107 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum
);
112 SparcLiveProcess::initState()
114 LiveProcess::initState();
116 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
117 // From the SPARC ABI
119 // Setup default FP state
120 tc
->setMiscRegNoEffect(MISCREG_FSR
, 0);
122 tc
->setMiscRegNoEffect(MISCREG_TICK
, 0);
125 * Register window management registers
128 // No windows contain info from other programs
129 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
130 tc
->setIntReg(NumIntArchRegs
+ 6, 0);
131 // There are no windows to pop
132 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
133 tc
->setIntReg(NumIntArchRegs
+ 4, 0);
134 // All windows are available to save into
135 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
136 tc
->setIntReg(NumIntArchRegs
+ 3, NWindows
- 2);
137 // All windows are "clean"
138 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
139 tc
->setIntReg(NumIntArchRegs
+ 5, NWindows
);
140 // Start with register window 0
141 tc
->setMiscReg(MISCREG_CWP
, 0);
142 // Always use spill and fill traps 0
143 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
144 tc
->setIntReg(NumIntArchRegs
+ 7, 0);
145 // Set the trap level to 0
146 tc
->setMiscRegNoEffect(MISCREG_TL
, 0);
147 // Set the ASI register to something fixed
148 tc
->setMiscReg(MISCREG_ASI
, ASI_PRIMARY
);
151 * T1 specific registers
153 // Turn on the icache, dcache, dtb translation, and itb translation.
154 tc
->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
, 15);
158 Sparc32LiveProcess::initState()
160 SparcLiveProcess::initState();
162 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
163 // The process runs in user mode with 32 bit addresses
167 tc
->setMiscReg(MISCREG_PSTATE
, pstate
);
169 argsInit(32 / 8, PageBytes
);
173 Sparc64LiveProcess::initState()
175 SparcLiveProcess::initState();
177 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
178 // The process runs in user mode
181 tc
->setMiscReg(MISCREG_PSTATE
, pstate
);
183 argsInit(sizeof(IntReg
), PageBytes
);
186 template<class IntType
>
188 SparcLiveProcess::argsInit(int pageSize
)
190 int intSize
= sizeof(IntType
);
192 typedef AuxVector
<IntType
> auxv_t
;
194 std::vector
<auxv_t
> auxv
;
202 // Even for a 32 bit process, the ABI says we still need to
203 // maintain double word alignment of the stack pointer.
206 // Patch the ld_bias for dynamic executables.
209 // load object file into target memory
210 objFile
->loadSections(initVirtMem
);
214 M5_HWCAP_SPARC_FLUSH
= 1,
215 M5_HWCAP_SPARC_STBAR
= 2,
216 M5_HWCAP_SPARC_SWAP
= 4,
217 M5_HWCAP_SPARC_MULDIV
= 8,
218 M5_HWCAP_SPARC_V9
= 16,
219 // This one should technically only be set
220 // if there is a cheetah or cheetah_plus tlb,
221 // but we'll use it all the time
222 M5_HWCAP_SPARC_ULTRA3
= 32
225 const int64_t hwcap
=
226 M5_HWCAP_SPARC_FLUSH
|
227 M5_HWCAP_SPARC_STBAR
|
228 M5_HWCAP_SPARC_SWAP
|
229 M5_HWCAP_SPARC_MULDIV
|
231 M5_HWCAP_SPARC_ULTRA3
;
233 // Setup the auxilliary vectors. These will already have endian conversion.
234 // Auxilliary vectors are loaded only for elf formatted executables.
235 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
237 // Bits which describe the system hardware capabilities
238 auxv
.push_back(auxv_t(M5_AT_HWCAP
, hwcap
));
239 // The system page size
240 auxv
.push_back(auxv_t(M5_AT_PAGESZ
, SparcISA::PageBytes
));
241 // Defined to be 100 in the kernel source.
242 // Frequency at which times() increments
243 auxv
.push_back(auxv_t(M5_AT_CLKTCK
, 100));
244 // For statically linked executables, this is the virtual address of the
245 // program header tables if they appear in the executable image
246 auxv
.push_back(auxv_t(M5_AT_PHDR
, elfObject
->programHeaderTable()));
247 // This is the size of a program header entry from the elf file.
248 auxv
.push_back(auxv_t(M5_AT_PHENT
, elfObject
->programHeaderSize()));
249 // This is the number of program headers from the original elf file.
250 auxv
.push_back(auxv_t(M5_AT_PHNUM
, elfObject
->programHeaderCount()));
251 // This is the base address of the ELF interpreter; it should be
252 // zero for static executables or contain the base address for
253 // dynamic executables.
254 auxv
.push_back(auxv_t(M5_AT_BASE
, getBias()));
255 // This is hardwired to 0 in the elf loading code in the kernel
256 auxv
.push_back(auxv_t(M5_AT_FLAGS
, 0));
257 // The entry point to the program
258 auxv
.push_back(auxv_t(M5_AT_ENTRY
, objFile
->entryPoint()));
259 // Different user and group IDs
260 auxv
.push_back(auxv_t(M5_AT_UID
, uid()));
261 auxv
.push_back(auxv_t(M5_AT_EUID
, euid()));
262 auxv
.push_back(auxv_t(M5_AT_GID
, gid()));
263 auxv
.push_back(auxv_t(M5_AT_EGID
, egid()));
264 // Whether to enable "secure mode" in the executable
265 auxv
.push_back(auxv_t(M5_AT_SECURE
, 0));
268 // Figure out how big the initial stack needs to be
270 // The unaccounted for 8 byte 0 at the top of the stack
273 // This is the name of the file which is present on the initial stack
274 // It's purpose is to let the user space linker examine the original file.
275 int file_name_size
= filename
.size() + 1;
277 int env_data_size
= 0;
278 for (int i
= 0; i
< envp
.size(); ++i
) {
279 env_data_size
+= envp
[i
].size() + 1;
281 int arg_data_size
= 0;
282 for (int i
= 0; i
< argv
.size(); ++i
) {
283 arg_data_size
+= argv
[i
].size() + 1;
287 int base_info_block_size
=
288 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
290 int info_block_size
= roundUp(base_info_block_size
, align
);
292 int info_block_padding
= info_block_size
- base_info_block_size
;
294 // Each auxilliary vector is two words
295 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
297 int envp_array_size
= intSize
* (envp
.size() + 1);
298 int argv_array_size
= intSize
* (argv
.size() + 1);
300 int argc_size
= intSize
;
301 int window_save_size
= intSize
* 16;
303 // Figure out the size of the contents of the actual initial frame
311 // There needs to be padding after the auxiliary vector data so that the
312 // very bottom of the stack is aligned properly.
313 int aligned_partial_size
= roundUp(frame_size
, align
);
314 int aux_padding
= aligned_partial_size
- frame_size
;
321 stack_min
= stack_base
- space_needed
;
322 stack_min
= roundDown(stack_min
, align
);
323 stack_size
= stack_base
- stack_min
;
325 // Allocate space for the stack
326 allocateMem(roundDown(stack_min
, pageSize
), roundUp(stack_size
, pageSize
));
328 // map out initial stack contents
329 IntType sentry_base
= stack_base
- sentry_size
;
330 IntType file_name_base
= sentry_base
- file_name_size
;
331 IntType env_data_base
= file_name_base
- env_data_size
;
332 IntType arg_data_base
= env_data_base
- arg_data_size
;
333 IntType auxv_array_base
= arg_data_base
-
334 info_block_padding
- aux_array_size
- aux_padding
;
335 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
336 IntType argv_array_base
= envp_array_base
- argv_array_size
;
337 IntType argc_base
= argv_array_base
- argc_size
;
339 IntType window_save_base
= argc_base
- window_save_size
;
342 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
343 DPRINTF(Stack
, "%#x - sentry NULL\n", sentry_base
);
344 DPRINTF(Stack
, "filename = %s\n", filename
);
345 DPRINTF(Stack
, "%#x - file name\n", file_name_base
);
346 DPRINTF(Stack
, "%#x - env data\n", env_data_base
);
347 DPRINTF(Stack
, "%#x - arg data\n", arg_data_base
);
348 DPRINTF(Stack
, "%#x - auxv array\n", auxv_array_base
);
349 DPRINTF(Stack
, "%#x - envp array\n", envp_array_base
);
350 DPRINTF(Stack
, "%#x - argv array\n", argv_array_base
);
351 DPRINTF(Stack
, "%#x - argc \n", argc_base
);
352 DPRINTF(Stack
, "%#x - window save\n", window_save_base
);
353 DPRINTF(Stack
, "%#x - stack min\n", stack_min
);
355 assert(window_save_base
== stack_min
);
357 // write contents to stack
360 IntType argc
= argv
.size();
361 IntType guestArgc
= SparcISA::htog(argc
);
363 // Write out the sentry void *
364 uint64_t sentry_NULL
= 0;
365 initVirtMem
.writeBlob(sentry_base
,
366 (uint8_t*)&sentry_NULL
, sentry_size
);
368 // Write the file name
369 initVirtMem
.writeString(file_name_base
, filename
.c_str());
371 // Copy the aux stuff
372 for (int x
= 0; x
< auxv
.size(); x
++) {
373 initVirtMem
.writeBlob(auxv_array_base
+ x
* 2 * intSize
,
374 (uint8_t*)&(auxv
[x
].a_type
), intSize
);
375 initVirtMem
.writeBlob(auxv_array_base
+ (x
* 2 + 1) * intSize
,
376 (uint8_t*)&(auxv
[x
].a_val
), intSize
);
379 // Write out the terminating zeroed auxilliary vector
380 const IntType zero
= 0;
381 initVirtMem
.writeBlob(auxv_array_base
+ intSize
* 2 * auxv
.size(),
382 (uint8_t*)&zero
, intSize
);
383 initVirtMem
.writeBlob(auxv_array_base
+ intSize
* (2 * auxv
.size() + 1),
384 (uint8_t*)&zero
, intSize
);
386 copyStringArray(envp
, envp_array_base
, env_data_base
, initVirtMem
);
387 copyStringArray(argv
, argv_array_base
, arg_data_base
, initVirtMem
);
389 initVirtMem
.writeBlob(argc_base
, (uint8_t*)&guestArgc
, intSize
);
391 // Set up space for the trap handlers into the processes address space.
392 // Since the stack grows down and there is reserved address space abov
393 // it, we can put stuff above it and stay out of the way.
394 fillStart
= stack_base
;
395 spillStart
= fillStart
+ sizeof(MachInst
) * numFillInsts
;
397 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
398 // Set up the thread context to start running the process
399 // assert(NumArgumentRegs >= 2);
400 // tc->setIntReg(ArgumentReg[0], argc);
401 // tc->setIntReg(ArgumentReg[1], argv_array_base);
402 tc
->setIntReg(StackPointerReg
, stack_min
- StackBias
);
404 // %g1 is a pointer to a function that should be run at exit. Since we
405 // don't have anything like that, it should be set to 0.
408 tc
->pcState(getStartPC());
410 // Align the "stack_min" to a page boundary.
411 stack_min
= roundDown(stack_min
, pageSize
);
417 Sparc64LiveProcess::argsInit(int intSize
, int pageSize
)
419 SparcLiveProcess::argsInit
<uint64_t>(pageSize
);
421 // Stuff the trap handlers into the process address space
422 initVirtMem
.writeBlob(fillStart
,
423 (uint8_t*)fillHandler64
, sizeof(MachInst
) * numFillInsts
);
424 initVirtMem
.writeBlob(spillStart
,
425 (uint8_t*)spillHandler64
, sizeof(MachInst
) * numSpillInsts
);
429 Sparc32LiveProcess::argsInit(int intSize
, int pageSize
)
431 SparcLiveProcess::argsInit
<uint32_t>(pageSize
);
433 // Stuff the trap handlers into the process address space
434 initVirtMem
.writeBlob(fillStart
,
435 (uint8_t*)fillHandler32
, sizeof(MachInst
) * numFillInsts
);
436 initVirtMem
.writeBlob(spillStart
,
437 (uint8_t*)spillHandler32
, sizeof(MachInst
) * numSpillInsts
);
440 void Sparc32LiveProcess::flushWindows(ThreadContext
*tc
)
442 IntReg Cansave
= tc
->readIntReg(NumIntArchRegs
+ 3);
443 IntReg Canrestore
= tc
->readIntReg(NumIntArchRegs
+ 4);
444 IntReg Otherwin
= tc
->readIntReg(NumIntArchRegs
+ 6);
445 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
446 MiscReg origCWP
= CWP
;
447 CWP
= (CWP
+ Cansave
+ 2) % NWindows
;
448 while (NWindows
- 2 - Cansave
!= 0) {
450 panic("Otherwin non-zero.\n");
452 tc
->setMiscReg(MISCREG_CWP
, CWP
);
454 IntReg sp
= tc
->readIntReg(StackPointerReg
);
455 for (int index
= 16; index
< 32; index
++) {
456 uint32_t regVal
= tc
->readIntReg(index
);
457 regVal
= htog(regVal
);
458 if (!tc
->getMemProxy().tryWriteBlob(
459 sp
+ (index
- 16) * 4, (uint8_t *)®Val
, 4)) {
460 warn("Failed to save register to the stack when "
461 "flushing windows.\n");
466 CWP
= (CWP
+ 1) % NWindows
;
469 tc
->setIntReg(NumIntArchRegs
+ 3, Cansave
);
470 tc
->setIntReg(NumIntArchRegs
+ 4, Canrestore
);
471 tc
->setMiscReg(MISCREG_CWP
, origCWP
);
475 Sparc64LiveProcess::flushWindows(ThreadContext
*tc
)
477 IntReg Cansave
= tc
->readIntReg(NumIntArchRegs
+ 3);
478 IntReg Canrestore
= tc
->readIntReg(NumIntArchRegs
+ 4);
479 IntReg Otherwin
= tc
->readIntReg(NumIntArchRegs
+ 6);
480 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
481 MiscReg origCWP
= CWP
;
482 CWP
= (CWP
+ Cansave
+ 2) % NWindows
;
483 while (NWindows
- 2 - Cansave
!= 0) {
485 panic("Otherwin non-zero.\n");
487 tc
->setMiscReg(MISCREG_CWP
, CWP
);
489 IntReg sp
= tc
->readIntReg(StackPointerReg
);
490 for (int index
= 16; index
< 32; index
++) {
491 IntReg regVal
= tc
->readIntReg(index
);
492 regVal
= htog(regVal
);
493 if (!tc
->getMemProxy().tryWriteBlob(
494 sp
+ 2047 + (index
- 16) * 8, (uint8_t *)®Val
, 8)) {
495 warn("Failed to save register to the stack when "
496 "flushing windows.\n");
501 CWP
= (CWP
+ 1) % NWindows
;
504 tc
->setIntReg(NumIntArchRegs
+ 3, Cansave
);
505 tc
->setIntReg(NumIntArchRegs
+ 4, Canrestore
);
506 tc
->setMiscReg(MISCREG_CWP
, origCWP
);
510 Sparc32LiveProcess::getSyscallArg(ThreadContext
*tc
, int &i
)
513 return bits(tc
->readIntReg(FirstArgumentReg
+ i
++), 31, 0);
517 Sparc32LiveProcess::setSyscallArg(ThreadContext
*tc
, int i
, IntReg val
)
520 tc
->setIntReg(FirstArgumentReg
+ i
, bits(val
, 31, 0));
524 Sparc64LiveProcess::getSyscallArg(ThreadContext
*tc
, int &i
)
527 return tc
->readIntReg(FirstArgumentReg
+ i
++);
531 Sparc64LiveProcess::setSyscallArg(ThreadContext
*tc
, int i
, IntReg val
)
534 tc
->setIntReg(FirstArgumentReg
+ i
, val
);
538 SparcLiveProcess::setSyscallReturn(ThreadContext
*tc
, SyscallReturn sysret
)
540 // check for error condition. SPARC syscall convention is to
541 // indicate success/failure in reg the carry bit of the ccr
542 // and put the return value itself in the standard return value reg ().
543 PSTATE pstate
= tc
->readMiscRegNoEffect(MISCREG_PSTATE
);
544 if (sysret
.successful()) {
545 // no error, clear XCC.C
546 tc
->setIntReg(NumIntArchRegs
+ 2,
547 tc
->readIntReg(NumIntArchRegs
+ 2) & 0xEE);
548 IntReg val
= sysret
.returnValue();
550 val
= bits(val
, 31, 0);
551 tc
->setIntReg(ReturnValueReg
, val
);
553 // got an error, set XCC.C
554 tc
->setIntReg(NumIntArchRegs
+ 2,
555 tc
->readIntReg(NumIntArchRegs
+ 2) | 0x11);
556 IntReg val
= sysret
.errnoValue();
558 val
= bits(val
, 31, 0);
559 tc
->setIntReg(ReturnValueReg
, val
);