2 * Copyright (c) 2003-2004 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "arch/sparc/asi.hh"
33 #include "arch/sparc/handlers.hh"
34 #include "arch/sparc/isa_traits.hh"
35 #include "arch/sparc/process.hh"
36 #include "arch/sparc/registers.hh"
37 #include "arch/sparc/types.hh"
38 #include "base/loader/elf_object.hh"
39 #include "base/loader/object_file.hh"
40 #include "base/misc.hh"
41 #include "cpu/thread_context.hh"
42 #include "debug/Stack.hh"
43 #include "mem/page_table.hh"
44 #include "mem/translating_port.hh"
45 #include "sim/process_impl.hh"
46 #include "sim/system.hh"
49 using namespace SparcISA
;
51 static const int FirstArgumentReg
= 8;
54 SparcLiveProcess::SparcLiveProcess(LiveProcessParams
* params
,
55 ObjectFile
*objFile
, Addr _StackBias
)
56 : LiveProcess(params
, objFile
), StackBias(_StackBias
)
59 // XXX all the below need to be updated for SPARC - Ali
60 brk_point
= objFile
->dataBase() + objFile
->dataSize() + objFile
->bssSize();
61 brk_point
= roundUp(brk_point
, VMPageSize
);
63 // Set pointer for next thread stack. Reserve 8M for main stack.
64 next_thread_stack_base
= stack_base
- (8 * 1024 * 1024);
66 // Initialize these to 0s
72 SparcLiveProcess::handleTrap(int trapNum
, ThreadContext
*tc
)
74 PCState pc
= tc
->pcState();
76 case 0x01: // Software breakpoint
77 warn("Software breakpoint encountered at pc %#x.\n", pc
.pc());
79 case 0x02: // Division by zero
80 warn("Software signaled a division by zero at pc %#x.\n", pc
.pc());
82 case 0x03: // Flush window trap
85 case 0x04: // Clean windows
86 warn("Ignoring process request for clean register "
87 "windows at pc %#x.\n", pc
.pc());
89 case 0x05: // Range check
90 warn("Software signaled a range check at pc %#x.\n", pc
.pc());
92 case 0x06: // Fix alignment
93 warn("Ignoring process request for os assisted unaligned accesses "
94 "at pc %#x.\n", pc
.pc());
96 case 0x07: // Integer overflow
97 warn("Software signaled an integer overflow at pc %#x.\n", pc
.pc());
99 case 0x32: // Get integer condition codes
100 warn("Ignoring process request to get the integer condition codes "
101 "at pc %#x.\n", pc
.pc());
103 case 0x33: // Set integer condition codes
104 warn("Ignoring process request to set the integer condition codes "
105 "at pc %#x.\n", pc
.pc());
108 panic("Unimplemented trap to operating system: trap number %#x.\n", trapNum
);
113 SparcLiveProcess::initState()
115 LiveProcess::initState();
117 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
118 // From the SPARC ABI
120 // Setup default FP state
121 tc
->setMiscRegNoEffect(MISCREG_FSR
, 0);
123 tc
->setMiscRegNoEffect(MISCREG_TICK
, 0);
126 * Register window management registers
129 // No windows contain info from other programs
130 // tc->setMiscRegNoEffect(MISCREG_OTHERWIN, 0);
131 tc
->setIntReg(NumIntArchRegs
+ 6, 0);
132 // There are no windows to pop
133 // tc->setMiscRegNoEffect(MISCREG_CANRESTORE, 0);
134 tc
->setIntReg(NumIntArchRegs
+ 4, 0);
135 // All windows are available to save into
136 // tc->setMiscRegNoEffect(MISCREG_CANSAVE, NWindows - 2);
137 tc
->setIntReg(NumIntArchRegs
+ 3, NWindows
- 2);
138 // All windows are "clean"
139 // tc->setMiscRegNoEffect(MISCREG_CLEANWIN, NWindows);
140 tc
->setIntReg(NumIntArchRegs
+ 5, NWindows
);
141 // Start with register window 0
142 tc
->setMiscReg(MISCREG_CWP
, 0);
143 // Always use spill and fill traps 0
144 // tc->setMiscRegNoEffect(MISCREG_WSTATE, 0);
145 tc
->setIntReg(NumIntArchRegs
+ 7, 0);
146 // Set the trap level to 0
147 tc
->setMiscRegNoEffect(MISCREG_TL
, 0);
148 // Set the ASI register to something fixed
149 tc
->setMiscRegNoEffect(MISCREG_ASI
, ASI_PRIMARY
);
152 * T1 specific registers
154 // Turn on the icache, dcache, dtb translation, and itb translation.
155 tc
->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL
, 15);
159 Sparc32LiveProcess::initState()
161 SparcLiveProcess::initState();
163 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
164 // The process runs in user mode with 32 bit addresses
165 tc
->setMiscReg(MISCREG_PSTATE
, 0x0a);
167 argsInit(32 / 8, VMPageSize
);
171 Sparc64LiveProcess::initState()
173 SparcLiveProcess::initState();
175 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
176 // The process runs in user mode
177 tc
->setMiscReg(MISCREG_PSTATE
, 0x02);
179 argsInit(sizeof(IntReg
), VMPageSize
);
182 template<class IntType
>
184 SparcLiveProcess::argsInit(int pageSize
)
186 int intSize
= sizeof(IntType
);
188 typedef AuxVector
<IntType
> auxv_t
;
190 std::vector
<auxv_t
> auxv
;
198 // Even for a 32 bit process, the ABI says we still need to
199 // maintain double word alignment of the stack pointer.
202 // load object file into target memory
203 objFile
->loadSections(initVirtMem
);
207 M5_HWCAP_SPARC_FLUSH
= 1,
208 M5_HWCAP_SPARC_STBAR
= 2,
209 M5_HWCAP_SPARC_SWAP
= 4,
210 M5_HWCAP_SPARC_MULDIV
= 8,
211 M5_HWCAP_SPARC_V9
= 16,
212 // This one should technically only be set
213 // if there is a cheetah or cheetah_plus tlb,
214 // but we'll use it all the time
215 M5_HWCAP_SPARC_ULTRA3
= 32
218 const int64_t hwcap
=
219 M5_HWCAP_SPARC_FLUSH
|
220 M5_HWCAP_SPARC_STBAR
|
221 M5_HWCAP_SPARC_SWAP
|
222 M5_HWCAP_SPARC_MULDIV
|
224 M5_HWCAP_SPARC_ULTRA3
;
226 // Setup the auxilliary vectors. These will already have endian conversion.
227 // Auxilliary vectors are loaded only for elf formatted executables.
228 ElfObject
* elfObject
= dynamic_cast<ElfObject
*>(objFile
);
230 // Bits which describe the system hardware capabilities
231 auxv
.push_back(auxv_t(M5_AT_HWCAP
, hwcap
));
232 // The system page size
233 auxv
.push_back(auxv_t(M5_AT_PAGESZ
, SparcISA::VMPageSize
));
234 // Defined to be 100 in the kernel source.
235 // Frequency at which times() increments
236 auxv
.push_back(auxv_t(M5_AT_CLKTCK
, 100));
237 // For statically linked executables, this is the virtual address of the
238 // program header tables if they appear in the executable image
239 auxv
.push_back(auxv_t(M5_AT_PHDR
, elfObject
->programHeaderTable()));
240 // This is the size of a program header entry from the elf file.
241 auxv
.push_back(auxv_t(M5_AT_PHENT
, elfObject
->programHeaderSize()));
242 // This is the number of program headers from the original elf file.
243 auxv
.push_back(auxv_t(M5_AT_PHNUM
, elfObject
->programHeaderCount()));
244 // This is the address of the elf "interpreter", It should be set
245 // to 0 for regular executables. It should be something else
246 // (not sure what) for dynamic libraries.
247 auxv
.push_back(auxv_t(M5_AT_BASE
, 0));
248 // This is hardwired to 0 in the elf loading code in the kernel
249 auxv
.push_back(auxv_t(M5_AT_FLAGS
, 0));
250 // The entry point to the program
251 auxv
.push_back(auxv_t(M5_AT_ENTRY
, objFile
->entryPoint()));
252 // Different user and group IDs
253 auxv
.push_back(auxv_t(M5_AT_UID
, uid()));
254 auxv
.push_back(auxv_t(M5_AT_EUID
, euid()));
255 auxv
.push_back(auxv_t(M5_AT_GID
, gid()));
256 auxv
.push_back(auxv_t(M5_AT_EGID
, egid()));
257 // Whether to enable "secure mode" in the executable
258 auxv
.push_back(auxv_t(M5_AT_SECURE
, 0));
261 // Figure out how big the initial stack needs to be
263 // The unaccounted for 8 byte 0 at the top of the stack
266 // This is the name of the file which is present on the initial stack
267 // It's purpose is to let the user space linker examine the original file.
268 int file_name_size
= filename
.size() + 1;
270 int env_data_size
= 0;
271 for (int i
= 0; i
< envp
.size(); ++i
) {
272 env_data_size
+= envp
[i
].size() + 1;
274 int arg_data_size
= 0;
275 for (int i
= 0; i
< argv
.size(); ++i
) {
276 arg_data_size
+= argv
[i
].size() + 1;
280 int base_info_block_size
=
281 sentry_size
+ file_name_size
+ env_data_size
+ arg_data_size
;
283 int info_block_size
= roundUp(base_info_block_size
, align
);
285 int info_block_padding
= info_block_size
- base_info_block_size
;
287 // Each auxilliary vector is two words
288 int aux_array_size
= intSize
* 2 * (auxv
.size() + 1);
290 int envp_array_size
= intSize
* (envp
.size() + 1);
291 int argv_array_size
= intSize
* (argv
.size() + 1);
293 int argc_size
= intSize
;
294 int window_save_size
= intSize
* 16;
296 // Figure out the size of the contents of the actual initial frame
304 // There needs to be padding after the auxiliary vector data so that the
305 // very bottom of the stack is aligned properly.
306 int aligned_partial_size
= roundUp(frame_size
, align
);
307 int aux_padding
= aligned_partial_size
- frame_size
;
314 stack_min
= stack_base
- space_needed
;
315 stack_min
= roundDown(stack_min
, align
);
316 stack_size
= stack_base
- stack_min
;
318 // Allocate space for the stack
319 allocateMem(roundDown(stack_min
, pageSize
), roundUp(stack_size
, pageSize
));
321 // map out initial stack contents
322 IntType sentry_base
= stack_base
- sentry_size
;
323 IntType file_name_base
= sentry_base
- file_name_size
;
324 IntType env_data_base
= file_name_base
- env_data_size
;
325 IntType arg_data_base
= env_data_base
- arg_data_size
;
326 IntType auxv_array_base
= arg_data_base
-
327 info_block_padding
- aux_array_size
- aux_padding
;
328 IntType envp_array_base
= auxv_array_base
- envp_array_size
;
329 IntType argv_array_base
= envp_array_base
- argv_array_size
;
330 IntType argc_base
= argv_array_base
- argc_size
;
332 IntType window_save_base
= argc_base
- window_save_size
;
335 DPRINTF(Stack
, "The addresses of items on the initial stack:\n");
336 DPRINTF(Stack
, "%#x - sentry NULL\n", sentry_base
);
337 DPRINTF(Stack
, "filename = %s\n", filename
);
338 DPRINTF(Stack
, "%#x - file name\n", file_name_base
);
339 DPRINTF(Stack
, "%#x - env data\n", env_data_base
);
340 DPRINTF(Stack
, "%#x - arg data\n", arg_data_base
);
341 DPRINTF(Stack
, "%#x - auxv array\n", auxv_array_base
);
342 DPRINTF(Stack
, "%#x - envp array\n", envp_array_base
);
343 DPRINTF(Stack
, "%#x - argv array\n", argv_array_base
);
344 DPRINTF(Stack
, "%#x - argc \n", argc_base
);
345 DPRINTF(Stack
, "%#x - window save\n", window_save_base
);
346 DPRINTF(Stack
, "%#x - stack min\n", stack_min
);
348 assert(window_save_base
== stack_min
);
350 // write contents to stack
353 IntType argc
= argv
.size();
354 IntType guestArgc
= SparcISA::htog(argc
);
356 // Write out the sentry void *
357 uint64_t sentry_NULL
= 0;
358 initVirtMem
->writeBlob(sentry_base
,
359 (uint8_t*)&sentry_NULL
, sentry_size
);
361 // Write the file name
362 initVirtMem
->writeString(file_name_base
, filename
.c_str());
364 // Copy the aux stuff
365 for (int x
= 0; x
< auxv
.size(); x
++) {
366 initVirtMem
->writeBlob(auxv_array_base
+ x
* 2 * intSize
,
367 (uint8_t*)&(auxv
[x
].a_type
), intSize
);
368 initVirtMem
->writeBlob(auxv_array_base
+ (x
* 2 + 1) * intSize
,
369 (uint8_t*)&(auxv
[x
].a_val
), intSize
);
372 // Write out the terminating zeroed auxilliary vector
373 const IntType zero
= 0;
374 initVirtMem
->writeBlob(auxv_array_base
+ intSize
* 2 * auxv
.size(),
375 (uint8_t*)&zero
, intSize
);
376 initVirtMem
->writeBlob(auxv_array_base
+ intSize
* (2 * auxv
.size() + 1),
377 (uint8_t*)&zero
, intSize
);
379 copyStringArray(envp
, envp_array_base
, env_data_base
, initVirtMem
);
380 copyStringArray(argv
, argv_array_base
, arg_data_base
, initVirtMem
);
382 initVirtMem
->writeBlob(argc_base
, (uint8_t*)&guestArgc
, intSize
);
384 // Set up space for the trap handlers into the processes address space.
385 // Since the stack grows down and there is reserved address space abov
386 // it, we can put stuff above it and stay out of the way.
387 fillStart
= stack_base
;
388 spillStart
= fillStart
+ sizeof(MachInst
) * numFillInsts
;
390 ThreadContext
*tc
= system
->getThreadContext(contextIds
[0]);
391 // Set up the thread context to start running the process
392 // assert(NumArgumentRegs >= 2);
393 // tc->setIntReg(ArgumentReg[0], argc);
394 // tc->setIntReg(ArgumentReg[1], argv_array_base);
395 tc
->setIntReg(StackPointerReg
, stack_min
- StackBias
);
397 // %g1 is a pointer to a function that should be run at exit. Since we
398 // don't have anything like that, it should be set to 0.
401 tc
->pcState(objFile
->entryPoint());
403 // Align the "stack_min" to a page boundary.
404 stack_min
= roundDown(stack_min
, pageSize
);
410 Sparc64LiveProcess::argsInit(int intSize
, int pageSize
)
412 SparcLiveProcess::argsInit
<uint64_t>(pageSize
);
414 // Stuff the trap handlers into the process address space
415 initVirtMem
->writeBlob(fillStart
,
416 (uint8_t*)fillHandler64
, sizeof(MachInst
) * numFillInsts
);
417 initVirtMem
->writeBlob(spillStart
,
418 (uint8_t*)spillHandler64
, sizeof(MachInst
) * numSpillInsts
);
422 Sparc32LiveProcess::argsInit(int intSize
, int pageSize
)
424 SparcLiveProcess::argsInit
<uint32_t>(pageSize
);
426 // Stuff the trap handlers into the process address space
427 initVirtMem
->writeBlob(fillStart
,
428 (uint8_t*)fillHandler32
, sizeof(MachInst
) * numFillInsts
);
429 initVirtMem
->writeBlob(spillStart
,
430 (uint8_t*)spillHandler32
, sizeof(MachInst
) * numSpillInsts
);
433 void Sparc32LiveProcess::flushWindows(ThreadContext
*tc
)
435 IntReg Cansave
= tc
->readIntReg(NumIntArchRegs
+ 3);
436 IntReg Canrestore
= tc
->readIntReg(NumIntArchRegs
+ 4);
437 IntReg Otherwin
= tc
->readIntReg(NumIntArchRegs
+ 6);
438 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
439 MiscReg origCWP
= CWP
;
440 CWP
= (CWP
+ Cansave
+ 2) % NWindows
;
441 while (NWindows
- 2 - Cansave
!= 0) {
443 panic("Otherwin non-zero.\n");
445 tc
->setMiscReg(MISCREG_CWP
, CWP
);
447 IntReg sp
= tc
->readIntReg(StackPointerReg
);
448 for (int index
= 16; index
< 32; index
++) {
449 uint32_t regVal
= tc
->readIntReg(index
);
450 regVal
= htog(regVal
);
451 if (!tc
->getMemPort()->tryWriteBlob(
452 sp
+ (index
- 16) * 4, (uint8_t *)®Val
, 4)) {
453 warn("Failed to save register to the stack when "
454 "flushing windows.\n");
459 CWP
= (CWP
+ 1) % NWindows
;
462 tc
->setIntReg(NumIntArchRegs
+ 3, Cansave
);
463 tc
->setIntReg(NumIntArchRegs
+ 4, Canrestore
);
464 tc
->setMiscReg(MISCREG_CWP
, origCWP
);
468 Sparc64LiveProcess::flushWindows(ThreadContext
*tc
)
470 IntReg Cansave
= tc
->readIntReg(NumIntArchRegs
+ 3);
471 IntReg Canrestore
= tc
->readIntReg(NumIntArchRegs
+ 4);
472 IntReg Otherwin
= tc
->readIntReg(NumIntArchRegs
+ 6);
473 MiscReg CWP
= tc
->readMiscReg(MISCREG_CWP
);
474 MiscReg origCWP
= CWP
;
475 CWP
= (CWP
+ Cansave
+ 2) % NWindows
;
476 while (NWindows
- 2 - Cansave
!= 0) {
478 panic("Otherwin non-zero.\n");
480 tc
->setMiscReg(MISCREG_CWP
, CWP
);
482 IntReg sp
= tc
->readIntReg(StackPointerReg
);
483 for (int index
= 16; index
< 32; index
++) {
484 IntReg regVal
= tc
->readIntReg(index
);
485 regVal
= htog(regVal
);
486 if (!tc
->getMemPort()->tryWriteBlob(
487 sp
+ 2047 + (index
- 16) * 8, (uint8_t *)®Val
, 8)) {
488 warn("Failed to save register to the stack when "
489 "flushing windows.\n");
494 CWP
= (CWP
+ 1) % NWindows
;
497 tc
->setIntReg(NumIntArchRegs
+ 3, Cansave
);
498 tc
->setIntReg(NumIntArchRegs
+ 4, Canrestore
);
499 tc
->setMiscReg(MISCREG_CWP
, origCWP
);
503 Sparc32LiveProcess::getSyscallArg(ThreadContext
*tc
, int &i
)
506 return bits(tc
->readIntReg(FirstArgumentReg
+ i
++), 31, 0);
510 Sparc32LiveProcess::setSyscallArg(ThreadContext
*tc
, int i
, IntReg val
)
513 tc
->setIntReg(FirstArgumentReg
+ i
, bits(val
, 31, 0));
517 Sparc64LiveProcess::getSyscallArg(ThreadContext
*tc
, int &i
)
520 return tc
->readIntReg(FirstArgumentReg
+ i
++);
524 Sparc64LiveProcess::setSyscallArg(ThreadContext
*tc
, int i
, IntReg val
)
527 tc
->setIntReg(FirstArgumentReg
+ i
, val
);
531 SparcLiveProcess::setSyscallReturn(ThreadContext
*tc
,
532 SyscallReturn return_value
)
534 // check for error condition. SPARC syscall convention is to
535 // indicate success/failure in reg the carry bit of the ccr
536 // and put the return value itself in the standard return value reg ().
537 if (return_value
.successful()) {
538 // no error, clear XCC.C
539 tc
->setIntReg(NumIntArchRegs
+ 2,
540 tc
->readIntReg(NumIntArchRegs
+ 2) & 0xEE);
541 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) & 0xEE);
542 IntReg val
= return_value
.value();
543 if (bits(tc
->readMiscRegNoEffect(
544 SparcISA::MISCREG_PSTATE
), 3, 3)) {
545 val
= bits(val
, 31, 0);
547 tc
->setIntReg(ReturnValueReg
, val
);
549 // got an error, set XCC.C
550 tc
->setIntReg(NumIntArchRegs
+ 2,
551 tc
->readIntReg(NumIntArchRegs
+ 2) | 0x11);
552 // tc->setMiscRegNoEffect(MISCREG_CCR, tc->readMiscRegNoEffect(MISCREG_CCR) | 0x11);
553 IntReg val
= -return_value
.value();
554 if (bits(tc
->readMiscRegNoEffect(
555 SparcISA::MISCREG_PSTATE
), 3, 3)) {
556 val
= bits(val
, 31, 0);
558 tc
->setIntReg(ReturnValueReg
, val
);