2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
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32 #include "arch/sparc/regfile.hh"
33 #include "cpu/thread_context.hh"
37 using namespace SparcISA
;
40 //RegFile class methods
41 Addr
RegFile::readPC()
46 void RegFile::setPC(Addr val
)
51 Addr
RegFile::readNextPC()
56 void RegFile::setNextPC(Addr val
)
61 Addr
RegFile::readNextNPC()
66 void RegFile::setNextNPC(Addr val
)
78 MiscReg
RegFile::readMiscReg(int miscReg
)
80 return miscRegFile
.readReg(miscReg
);
83 MiscReg
RegFile::readMiscRegWithEffect(int miscReg
, ThreadContext
*tc
)
85 return miscRegFile
.readRegWithEffect(miscReg
, tc
);
88 void RegFile::setMiscReg(int miscReg
, const MiscReg
&val
)
90 miscRegFile
.setReg(miscReg
, val
);
93 void RegFile::setMiscRegWithEffect(int miscReg
, const MiscReg
&val
,
96 miscRegFile
.setRegWithEffect(miscReg
, val
, tc
);
99 FloatReg
RegFile::readFloatReg(int floatReg
, int width
)
101 return floatRegFile
.readReg(floatReg
, width
);
104 FloatReg
RegFile::readFloatReg(int floatReg
)
106 //Use the "natural" width of a single float
107 return floatRegFile
.readReg(floatReg
, FloatRegFile::SingleWidth
);
110 FloatRegBits
RegFile::readFloatRegBits(int floatReg
, int width
)
112 return floatRegFile
.readRegBits(floatReg
, width
);
115 FloatRegBits
RegFile::readFloatRegBits(int floatReg
)
117 //Use the "natural" width of a single float
118 return floatRegFile
.readRegBits(floatReg
,
119 FloatRegFile::SingleWidth
);
122 void RegFile::setFloatReg(int floatReg
, const FloatReg
&val
, int width
)
124 floatRegFile
.setReg(floatReg
, val
, width
);
127 void RegFile::setFloatReg(int floatReg
, const FloatReg
&val
)
129 //Use the "natural" width of a single float
130 setFloatReg(floatReg
, val
, FloatRegFile::SingleWidth
);
133 void RegFile::setFloatRegBits(int floatReg
, const FloatRegBits
&val
, int width
)
135 floatRegFile
.setRegBits(floatReg
, val
, width
);
138 void RegFile::setFloatRegBits(int floatReg
, const FloatRegBits
&val
)
140 //Use the "natural" width of a single float
141 floatRegFile
.setRegBits(floatReg
, val
, FloatRegFile::SingleWidth
);
144 IntReg
RegFile::readIntReg(int intReg
)
146 return intRegFile
.readReg(intReg
);
149 void RegFile::setIntReg(int intReg
, const IntReg
&val
)
151 intRegFile
.setReg(intReg
, val
);
154 int SparcISA::flattenIntIndex(ThreadContext
* tc
, int reg
)
156 int gl
= tc
->readMiscReg(MISCREG_GL
);
157 int cwp
= tc
->readMiscReg(MISCREG_CWP
);
158 //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
163 //Put it in the appropriate set of globals
164 newReg
= reg
+ gl
* 8;
166 else if(reg
< NumIntArchRegs
)
168 //Regular windowed register
169 //Put it in the window pointed to by cwp
171 ((reg
- 8 - cwp
* 16 + NWindows
* 16) % (NWindows
* 16));
173 else if(reg
< NumIntArchRegs
+ NumMicroIntRegs
)
176 //Displace from the end of the regular registers
177 newReg
= reg
- NumIntArchRegs
+ MaxGL
* 8 + NWindows
* 16;
179 else if(reg
< 2 * NumIntArchRegs
+ NumMicroIntRegs
)
181 reg
-= (NumIntArchRegs
+ NumMicroIntRegs
);
184 //Global register from the next window
185 //Put it in the appropriate set of globals
186 newReg
= reg
+ gl
* 8;
190 //Windowed register from the previous window
191 //Put it in the window before the one pointed to by cwp
193 ((reg
- 8 - (cwp
- 1) * 16 + NWindows
* 16) % (NWindows
* 16));
196 else if(reg
< 3 * NumIntArchRegs
+ NumMicroIntRegs
)
198 reg
-= (2 * NumIntArchRegs
+ NumMicroIntRegs
);
201 //Global register from the previous window
202 //Put it in the appropriate set of globals
203 newReg
= reg
+ gl
* 8;
207 //Windowed register from the next window
208 //Put it in the window after the one pointed to by cwp
210 ((reg
- 8 - (cwp
+ 1) * 16 + NWindows
* 16) % (NWindows
* 16));
214 panic("Tried to flatten invalid register index %d!\n", reg
);
215 DPRINTF(Sparc
, "Flattened register %d to %d.\n", reg
, newReg
);
217 //return intRegFile.flattenIndex(reg);
220 void RegFile::serialize(std::ostream
&os
)
222 intRegFile
.serialize(os
);
223 floatRegFile
.serialize(os
);
224 miscRegFile
.serialize(os
);
225 SERIALIZE_SCALAR(pc
);
226 SERIALIZE_SCALAR(npc
);
229 void RegFile::unserialize(Checkpoint
*cp
, const std::string
§ion
)
231 intRegFile
.unserialize(cp
, section
);
232 floatRegFile
.unserialize(cp
, section
);
233 miscRegFile
.unserialize(cp
, section
);
234 UNSERIALIZE_SCALAR(pc
);
235 UNSERIALIZE_SCALAR(npc
);
238 void RegFile::changeContext(RegContextParam param
, RegContextVal val
)
243 intRegFile
.setCWP(val
);
245 case CONTEXT_GLOBALS
:
246 intRegFile
.setGlobals(val
);
249 panic("Tried to set illegal context parameter in the SPARC regfile.\n");
253 int SparcISA::InterruptLevel(uint64_t softint
)
255 if (softint
& 0x10000 || softint
& 0x1)
259 while (level
> 0 && !(1 << level
& softint
))
261 if (1 << level
& softint
)
266 void SparcISA::copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
269 uint8_t tl
= src
->readMiscReg(MISCREG_TL
);
271 // Read all the trap level dependent registers and save them off
272 for(int i
= 1; i
<= MaxTL
; i
++)
274 src
->setMiscReg(MISCREG_TL
, i
);
275 dest
->setMiscReg(MISCREG_TL
, i
);
277 dest
->setMiscReg(MISCREG_TT
, src
->readMiscReg(MISCREG_TT
));
278 dest
->setMiscReg(MISCREG_TPC
, src
->readMiscReg(MISCREG_TPC
));
279 dest
->setMiscReg(MISCREG_TNPC
, src
->readMiscReg(MISCREG_TNPC
));
280 dest
->setMiscReg(MISCREG_TSTATE
, src
->readMiscReg(MISCREG_TSTATE
));
283 // Save off the traplevel
284 dest
->setMiscReg(MISCREG_TL
, tl
);
285 src
->setMiscReg(MISCREG_TL
, tl
);
289 // dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
290 // dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
291 dest
->setMiscReg(MISCREG_ASI
, src
->readMiscReg(MISCREG_ASI
));
292 dest
->setMiscReg(MISCREG_TICK
, src
->readMiscReg(MISCREG_TICK
));
293 dest
->setMiscReg(MISCREG_FPRS
, src
->readMiscReg(MISCREG_FPRS
));
294 dest
->setMiscReg(MISCREG_SOFTINT
, src
->readMiscReg(MISCREG_SOFTINT
));
295 dest
->setMiscReg(MISCREG_TICK_CMPR
, src
->readMiscReg(MISCREG_TICK_CMPR
));
296 dest
->setMiscReg(MISCREG_STICK
, src
->readMiscReg(MISCREG_STICK
));
297 dest
->setMiscReg(MISCREG_STICK_CMPR
, src
->readMiscReg(MISCREG_STICK_CMPR
));
300 dest
->setMiscReg(MISCREG_TICK
, src
->readMiscReg(MISCREG_TICK
));
301 dest
->setMiscReg(MISCREG_TBA
, src
->readMiscReg(MISCREG_TBA
));
302 dest
->setMiscReg(MISCREG_PSTATE
, src
->readMiscReg(MISCREG_PSTATE
));
303 dest
->setMiscReg(MISCREG_PIL
, src
->readMiscReg(MISCREG_PIL
));
304 dest
->setMiscReg(MISCREG_CWP
, src
->readMiscReg(MISCREG_CWP
));
305 // dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
306 // dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
307 // dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
308 // dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
309 // dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
310 dest
->setMiscReg(MISCREG_GL
, src
->readMiscReg(MISCREG_GL
));
312 // Hyperprivilged registers
313 dest
->setMiscReg(MISCREG_HPSTATE
, src
->readMiscReg(MISCREG_HPSTATE
));
314 dest
->setMiscReg(MISCREG_HINTP
, src
->readMiscReg(MISCREG_HINTP
));
315 dest
->setMiscReg(MISCREG_HTBA
, src
->readMiscReg(MISCREG_HTBA
));
316 dest
->setMiscReg(MISCREG_STRAND_STS_REG
,
317 src
->readMiscReg(MISCREG_STRAND_STS_REG
));
318 dest
->setMiscReg(MISCREG_HSTICK_CMPR
,
319 src
->readMiscReg(MISCREG_HSTICK_CMPR
));
322 dest
->setMiscReg(MISCREG_FSR
, src
->readMiscReg(MISCREG_FSR
));
324 //Strand Status Register
325 dest
->setMiscReg(MISCREG_STRAND_STS_REG
,
326 src
->readMiscReg(MISCREG_STRAND_STS_REG
));
329 dest
->setMiscReg(MISCREG_MMU_P_CONTEXT
,
330 src
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
331 dest
->setMiscReg(MISCREG_MMU_S_CONTEXT
,
332 src
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
333 dest
->setMiscReg(MISCREG_MMU_PART_ID
,
334 src
->readMiscReg(MISCREG_MMU_PART_ID
));
335 dest
->setMiscReg(MISCREG_MMU_LSU_CTRL
,
336 src
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
338 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
,
339 src
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
));
340 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
,
341 src
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
));
342 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
,
343 src
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
));
344 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
,
345 src
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
));
346 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
,
347 src
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
));
348 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
,
349 src
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
));
350 dest
->setMiscReg(MISCREG_MMU_ITLB_SFSR
,
351 src
->readMiscReg(MISCREG_MMU_ITLB_SFSR
));
352 dest
->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
,
353 src
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
));
355 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
,
356 src
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
));
357 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
,
358 src
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
));
359 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
,
360 src
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
));
361 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
,
362 src
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
));
363 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
,
364 src
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
));
365 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
,
366 src
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
));
367 dest
->setMiscReg(MISCREG_MMU_DTLB_SFSR
,
368 src
->readMiscReg(MISCREG_MMU_DTLB_SFSR
));
369 dest
->setMiscReg(MISCREG_MMU_DTLB_SFAR
,
370 src
->readMiscReg(MISCREG_MMU_DTLB_SFAR
));
371 dest
->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
,
372 src
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
));
374 // Scratchpad Registers
375 dest
->setMiscReg(MISCREG_SCRATCHPAD_R0
,
376 src
->readMiscReg(MISCREG_SCRATCHPAD_R0
));
377 dest
->setMiscReg(MISCREG_SCRATCHPAD_R1
,
378 src
->readMiscReg(MISCREG_SCRATCHPAD_R1
));
379 dest
->setMiscReg(MISCREG_SCRATCHPAD_R2
,
380 src
->readMiscReg(MISCREG_SCRATCHPAD_R2
));
381 dest
->setMiscReg(MISCREG_SCRATCHPAD_R3
,
382 src
->readMiscReg(MISCREG_SCRATCHPAD_R3
));
383 dest
->setMiscReg(MISCREG_SCRATCHPAD_R4
,
384 src
->readMiscReg(MISCREG_SCRATCHPAD_R4
));
385 dest
->setMiscReg(MISCREG_SCRATCHPAD_R5
,
386 src
->readMiscReg(MISCREG_SCRATCHPAD_R5
));
387 dest
->setMiscReg(MISCREG_SCRATCHPAD_R6
,
388 src
->readMiscReg(MISCREG_SCRATCHPAD_R6
));
389 dest
->setMiscReg(MISCREG_SCRATCHPAD_R7
,
390 src
->readMiscReg(MISCREG_SCRATCHPAD_R7
));
393 dest
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
,
394 src
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
));
395 dest
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL
,
396 src
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL
));
397 dest
->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD
,
398 src
->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD
));
399 dest
->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL
,
400 src
->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL
));
401 dest
->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD
,
402 src
->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD
));
403 dest
->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL
,
404 src
->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL
));
405 dest
->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD
,
406 src
->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD
));
407 dest
->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL
,
408 src
->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL
));
411 void SparcISA::copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
413 // First loop through the integer registers.
414 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
415 dest
->setIntReg(i
, src
->readIntReg(i
));
418 // Then loop through the floating point registers.
419 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
420 dest
->setFloatRegBits(i
, src
->readFloatRegBits(i
));
423 // Copy misc. registers
424 copyMiscRegs(src
, dest
);
426 // Lastly copy PC/NPC
427 dest
->setPC(src
->readPC());
428 dest
->setNextPC(src
->readNextPC());
429 dest
->setNextNPC(src
->readNextNPC());