2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
32 #include "arch/sparc/regfile.hh"
33 #include "cpu/thread_context.hh"
37 using namespace SparcISA
;
40 //RegFile class methods
41 Addr
RegFile::readPC()
46 void RegFile::setPC(Addr val
)
51 Addr
RegFile::readNextPC()
56 void RegFile::setNextPC(Addr val
)
61 Addr
RegFile::readNextNPC()
66 void RegFile::setNextNPC(Addr val
)
78 MiscReg
RegFile::readMiscReg(int miscReg
)
80 return miscRegFile
.readReg(miscReg
);
83 MiscReg
RegFile::readMiscRegWithEffect(int miscReg
, ThreadContext
*tc
)
85 return miscRegFile
.readRegWithEffect(miscReg
, tc
);
88 void RegFile::setMiscReg(int miscReg
, const MiscReg
&val
)
90 miscRegFile
.setReg(miscReg
, val
);
93 void RegFile::setMiscRegWithEffect(int miscReg
, const MiscReg
&val
,
96 miscRegFile
.setRegWithEffect(miscReg
, val
, tc
);
99 FloatReg
RegFile::readFloatReg(int floatReg
, int width
)
101 return floatRegFile
.readReg(floatReg
, width
);
104 FloatReg
RegFile::readFloatReg(int floatReg
)
106 //Use the "natural" width of a single float
107 return floatRegFile
.readReg(floatReg
, FloatRegFile::SingleWidth
);
110 FloatRegBits
RegFile::readFloatRegBits(int floatReg
, int width
)
112 return floatRegFile
.readRegBits(floatReg
, width
);
115 FloatRegBits
RegFile::readFloatRegBits(int floatReg
)
117 //Use the "natural" width of a single float
118 return floatRegFile
.readRegBits(floatReg
,
119 FloatRegFile::SingleWidth
);
122 void RegFile::setFloatReg(int floatReg
, const FloatReg
&val
, int width
)
124 floatRegFile
.setReg(floatReg
, val
, width
);
127 void RegFile::setFloatReg(int floatReg
, const FloatReg
&val
)
129 //Use the "natural" width of a single float
130 setFloatReg(floatReg
, val
, FloatRegFile::SingleWidth
);
133 void RegFile::setFloatRegBits(int floatReg
, const FloatRegBits
&val
, int width
)
135 floatRegFile
.setRegBits(floatReg
, val
, width
);
138 void RegFile::setFloatRegBits(int floatReg
, const FloatRegBits
&val
)
140 //Use the "natural" width of a single float
141 floatRegFile
.setRegBits(floatReg
, val
, FloatRegFile::SingleWidth
);
144 IntReg
RegFile::readIntReg(int intReg
)
146 return intRegFile
.readReg(intReg
);
149 void RegFile::setIntReg(int intReg
, const IntReg
&val
)
151 intRegFile
.setReg(intReg
, val
);
154 int SparcISA::flattenIntIndex(ThreadContext
* tc
, int reg
)
156 int gl
= tc
->readMiscReg(MISCREG_GL
);
157 int cwp
= tc
->readMiscReg(MISCREG_CWP
);
158 //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
160 //The total number of global registers
161 int numGlobals
= (MaxGL
+ 1) * 8;
165 //Put it in the appropriate set of globals
166 newReg
= reg
+ gl
* 8;
168 else if(reg
< NumIntArchRegs
)
170 //Regular windowed register
171 //Put it in the window pointed to by cwp
172 newReg
= numGlobals
+
173 ((reg
- 8 - cwp
* 16 + NWindows
* 16) % (NWindows
* 16));
175 else if(reg
< NumIntArchRegs
+ NumMicroIntRegs
)
178 //Displace from the end of the regular registers
179 newReg
= reg
- NumIntArchRegs
+ numGlobals
+ NWindows
* 16;
181 else if(reg
< 2 * NumIntArchRegs
+ NumMicroIntRegs
)
183 reg
-= (NumIntArchRegs
+ NumMicroIntRegs
);
186 //Global register from the next window
187 //Put it in the appropriate set of globals
188 newReg
= reg
+ gl
* 8;
192 //Windowed register from the previous window
193 //Put it in the window before the one pointed to by cwp
194 newReg
= numGlobals
+
195 ((reg
- 8 - (cwp
- 1) * 16 + NWindows
* 16) % (NWindows
* 16));
198 else if(reg
< 3 * NumIntArchRegs
+ NumMicroIntRegs
)
200 reg
-= (2 * NumIntArchRegs
+ NumMicroIntRegs
);
203 //Global register from the previous window
204 //Put it in the appropriate set of globals
205 newReg
= reg
+ gl
* 8;
209 //Windowed register from the next window
210 //Put it in the window after the one pointed to by cwp
211 newReg
= numGlobals
+
212 ((reg
- 8 - (cwp
+ 1) * 16 + NWindows
* 16) % (NWindows
* 16));
216 panic("Tried to flatten invalid register index %d!\n", reg
);
217 DPRINTF(Sparc
, "Flattened register %d to %d.\n", reg
, newReg
);
219 //return intRegFile.flattenIndex(reg);
222 void RegFile::serialize(std::ostream
&os
)
224 intRegFile
.serialize(os
);
225 floatRegFile
.serialize(os
);
226 miscRegFile
.serialize(os
);
227 SERIALIZE_SCALAR(pc
);
228 SERIALIZE_SCALAR(npc
);
229 SERIALIZE_SCALAR(nnpc
);
232 void RegFile::unserialize(Checkpoint
*cp
, const std::string
§ion
)
234 intRegFile
.unserialize(cp
, section
);
235 floatRegFile
.unserialize(cp
, section
);
236 miscRegFile
.unserialize(cp
, section
);
237 UNSERIALIZE_SCALAR(pc
);
238 UNSERIALIZE_SCALAR(npc
);
239 UNSERIALIZE_SCALAR(nnpc
);
242 void RegFile::changeContext(RegContextParam param
, RegContextVal val
)
247 intRegFile
.setCWP(val
);
249 case CONTEXT_GLOBALS
:
250 intRegFile
.setGlobals(val
);
253 panic("Tried to set illegal context parameter in the SPARC regfile.\n");
257 int SparcISA::InterruptLevel(uint64_t softint
)
259 if (softint
& 0x10000 || softint
& 0x1)
263 while (level
> 0 && !(1 << level
& softint
))
265 if (1 << level
& softint
)
270 void SparcISA::copyMiscRegs(ThreadContext
*src
, ThreadContext
*dest
)
273 uint8_t tl
= src
->readMiscReg(MISCREG_TL
);
275 // Read all the trap level dependent registers and save them off
276 for(int i
= 1; i
<= MaxTL
; i
++)
278 src
->setMiscReg(MISCREG_TL
, i
);
279 dest
->setMiscReg(MISCREG_TL
, i
);
281 dest
->setMiscReg(MISCREG_TT
, src
->readMiscReg(MISCREG_TT
));
282 dest
->setMiscReg(MISCREG_TPC
, src
->readMiscReg(MISCREG_TPC
));
283 dest
->setMiscReg(MISCREG_TNPC
, src
->readMiscReg(MISCREG_TNPC
));
284 dest
->setMiscReg(MISCREG_TSTATE
, src
->readMiscReg(MISCREG_TSTATE
));
287 // Save off the traplevel
288 dest
->setMiscReg(MISCREG_TL
, tl
);
289 src
->setMiscReg(MISCREG_TL
, tl
);
293 // dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
294 // dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
295 dest
->setMiscReg(MISCREG_ASI
, src
->readMiscReg(MISCREG_ASI
));
296 dest
->setMiscReg(MISCREG_TICK
, src
->readMiscReg(MISCREG_TICK
));
297 dest
->setMiscReg(MISCREG_FPRS
, src
->readMiscReg(MISCREG_FPRS
));
298 dest
->setMiscReg(MISCREG_SOFTINT
, src
->readMiscReg(MISCREG_SOFTINT
));
299 dest
->setMiscReg(MISCREG_TICK_CMPR
, src
->readMiscReg(MISCREG_TICK_CMPR
));
300 dest
->setMiscReg(MISCREG_STICK
, src
->readMiscReg(MISCREG_STICK
));
301 dest
->setMiscReg(MISCREG_STICK_CMPR
, src
->readMiscReg(MISCREG_STICK_CMPR
));
304 dest
->setMiscReg(MISCREG_TICK
, src
->readMiscReg(MISCREG_TICK
));
305 dest
->setMiscReg(MISCREG_TBA
, src
->readMiscReg(MISCREG_TBA
));
306 dest
->setMiscReg(MISCREG_PSTATE
, src
->readMiscReg(MISCREG_PSTATE
));
307 dest
->setMiscReg(MISCREG_PIL
, src
->readMiscReg(MISCREG_PIL
));
308 dest
->setMiscReg(MISCREG_CWP
, src
->readMiscReg(MISCREG_CWP
));
309 // dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
310 // dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
311 // dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
312 // dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
313 // dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
314 dest
->setMiscReg(MISCREG_GL
, src
->readMiscReg(MISCREG_GL
));
316 // Hyperprivilged registers
317 dest
->setMiscReg(MISCREG_HPSTATE
, src
->readMiscReg(MISCREG_HPSTATE
));
318 dest
->setMiscReg(MISCREG_HINTP
, src
->readMiscReg(MISCREG_HINTP
));
319 dest
->setMiscReg(MISCREG_HTBA
, src
->readMiscReg(MISCREG_HTBA
));
320 dest
->setMiscReg(MISCREG_STRAND_STS_REG
,
321 src
->readMiscReg(MISCREG_STRAND_STS_REG
));
322 dest
->setMiscReg(MISCREG_HSTICK_CMPR
,
323 src
->readMiscReg(MISCREG_HSTICK_CMPR
));
326 dest
->setMiscReg(MISCREG_FSR
, src
->readMiscReg(MISCREG_FSR
));
328 //Strand Status Register
329 dest
->setMiscReg(MISCREG_STRAND_STS_REG
,
330 src
->readMiscReg(MISCREG_STRAND_STS_REG
));
333 dest
->setMiscReg(MISCREG_MMU_P_CONTEXT
,
334 src
->readMiscReg(MISCREG_MMU_P_CONTEXT
));
335 dest
->setMiscReg(MISCREG_MMU_S_CONTEXT
,
336 src
->readMiscReg(MISCREG_MMU_S_CONTEXT
));
337 dest
->setMiscReg(MISCREG_MMU_PART_ID
,
338 src
->readMiscReg(MISCREG_MMU_PART_ID
));
339 dest
->setMiscReg(MISCREG_MMU_LSU_CTRL
,
340 src
->readMiscReg(MISCREG_MMU_LSU_CTRL
));
342 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
,
343 src
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0
));
344 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
,
345 src
->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1
));
346 dest
->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
,
347 src
->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG
));
348 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
,
349 src
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0
));
350 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
,
351 src
->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1
));
352 dest
->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
,
353 src
->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG
));
354 dest
->setMiscReg(MISCREG_MMU_ITLB_SFSR
,
355 src
->readMiscReg(MISCREG_MMU_ITLB_SFSR
));
356 dest
->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
,
357 src
->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS
));
359 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
,
360 src
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0
));
361 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
,
362 src
->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1
));
363 dest
->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
,
364 src
->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG
));
365 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
,
366 src
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0
));
367 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
,
368 src
->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1
));
369 dest
->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
,
370 src
->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG
));
371 dest
->setMiscReg(MISCREG_MMU_DTLB_SFSR
,
372 src
->readMiscReg(MISCREG_MMU_DTLB_SFSR
));
373 dest
->setMiscReg(MISCREG_MMU_DTLB_SFAR
,
374 src
->readMiscReg(MISCREG_MMU_DTLB_SFAR
));
375 dest
->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
,
376 src
->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS
));
378 // Scratchpad Registers
379 dest
->setMiscReg(MISCREG_SCRATCHPAD_R0
,
380 src
->readMiscReg(MISCREG_SCRATCHPAD_R0
));
381 dest
->setMiscReg(MISCREG_SCRATCHPAD_R1
,
382 src
->readMiscReg(MISCREG_SCRATCHPAD_R1
));
383 dest
->setMiscReg(MISCREG_SCRATCHPAD_R2
,
384 src
->readMiscReg(MISCREG_SCRATCHPAD_R2
));
385 dest
->setMiscReg(MISCREG_SCRATCHPAD_R3
,
386 src
->readMiscReg(MISCREG_SCRATCHPAD_R3
));
387 dest
->setMiscReg(MISCREG_SCRATCHPAD_R4
,
388 src
->readMiscReg(MISCREG_SCRATCHPAD_R4
));
389 dest
->setMiscReg(MISCREG_SCRATCHPAD_R5
,
390 src
->readMiscReg(MISCREG_SCRATCHPAD_R5
));
391 dest
->setMiscReg(MISCREG_SCRATCHPAD_R6
,
392 src
->readMiscReg(MISCREG_SCRATCHPAD_R6
));
393 dest
->setMiscReg(MISCREG_SCRATCHPAD_R7
,
394 src
->readMiscReg(MISCREG_SCRATCHPAD_R7
));
397 dest
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
,
398 src
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD
));
399 dest
->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL
,
400 src
->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL
));
401 dest
->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD
,
402 src
->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD
));
403 dest
->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL
,
404 src
->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL
));
405 dest
->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD
,
406 src
->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD
));
407 dest
->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL
,
408 src
->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL
));
409 dest
->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD
,
410 src
->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD
));
411 dest
->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL
,
412 src
->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL
));
415 void SparcISA::copyRegs(ThreadContext
*src
, ThreadContext
*dest
)
417 // First loop through the integer registers.
418 for (int i
= 0; i
< TheISA::NumIntRegs
; ++i
) {
419 dest
->setIntReg(i
, src
->readIntReg(i
));
422 // Then loop through the floating point registers.
423 for (int i
= 0; i
< TheISA::NumFloatRegs
; ++i
) {
424 dest
->setFloatRegBits(i
, src
->readFloatRegBits(i
));
427 // Copy misc. registers
428 copyMiscRegs(src
, dest
);
430 // Lastly copy PC/NPC
431 dest
->setPC(src
->readPC());
432 dest
->setNextPC(src
->readNextPC());
433 dest
->setNextNPC(src
->readNextNPC());