src/arch/sparc/regfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/regfile.hh"
  33 #include "cpu/thread_context.hh"
  34
  35 class Checkpoint;
  36
  37 using namespace SparcISA;
  38 using namespace std;
  39
  40 //RegFile class methods
  41 Addr RegFile::readPC()
  42 {
  43     return pc;
  44 }
  45
  46 void RegFile::setPC(Addr val)
  47 {
  48     pc = val;
  49 }
  50
  51 Addr RegFile::readNextPC()
  52 {
  53     return npc;
  54 }
  55
  56 void RegFile::setNextPC(Addr val)
  57 {
  58     npc = val;
  59 }
  60
  61 Addr RegFile::readNextNPC()
  62 {
  63     return nnpc;
  64 }
  65
  66 void RegFile::setNextNPC(Addr val)
  67 {
  68     nnpc = val;
  69 }
  70
  71 void RegFile::clear()
  72 {
  73     floatRegFile.clear();
  74     intRegFile.clear();
  75     miscRegFile.clear();
  76 }
  77
  78 MiscReg RegFile::readMiscReg(int miscReg)
  79 {
  80     return miscRegFile.readReg(miscReg);
  81 }
  82
  83 MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
  84 {
  85     return miscRegFile.readRegWithEffect(miscReg, tc);
  86 }
  87
  88 void RegFile::setMiscReg(int miscReg, const MiscReg &val)
  89 {
  90     miscRegFile.setReg(miscReg, val);
  91 }
  92
  93 void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
  94         ThreadContext * tc)
  95 {
  96     miscRegFile.setRegWithEffect(miscReg, val, tc);
  97 }
  98
  99 FloatReg RegFile::readFloatReg(int floatReg, int width)
 100 {
 101     return floatRegFile.readReg(floatReg, width);
 102 }
 103
 104 FloatReg RegFile::readFloatReg(int floatReg)
 105 {
 106     //Use the "natural" width of a single float
 107     return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
 108 }
 109
 110 FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
 111 {
 112     return floatRegFile.readRegBits(floatReg, width);
 113 }
 114
 115 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 116 {
 117     //Use the "natural" width of a single float
 118     return floatRegFile.readRegBits(floatReg,
 119             FloatRegFile::SingleWidth);
 120 }
 121
 122 void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
 123 {
 124     floatRegFile.setReg(floatReg, val, width);
 125 }
 126
 127 void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 128 {
 129     //Use the "natural" width of a single float
 130     setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
 131 }
 132
 133 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 134 {
 135     floatRegFile.setRegBits(floatReg, val, width);
 136 }
 137
 138 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 139 {
 140     //Use the "natural" width of a single float
 141     floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 142 }
 143
 144 IntReg RegFile::readIntReg(int intReg)
 145 {
 146     return intRegFile.readReg(intReg);
 147 }
 148
 149 void RegFile::setIntReg(int intReg, const IntReg &val)
 150 {
 151     intRegFile.setReg(intReg, val);
 152 }
 153
 154 void RegFile::serialize(std::ostream &os)
 155 {
 156     intRegFile.serialize(os);
 157     floatRegFile.serialize(os);
 158     miscRegFile.serialize(os);
 159     SERIALIZE_SCALAR(pc);
 160     SERIALIZE_SCALAR(npc);
 161 }
 162
 163 void RegFile::unserialize(Checkpoint *cp, const std::string &section)
 164 {
 165     intRegFile.unserialize(cp, section);
 166     floatRegFile.unserialize(cp, section);
 167     miscRegFile.unserialize(cp, section);
 168     UNSERIALIZE_SCALAR(pc);
 169     UNSERIALIZE_SCALAR(npc);
 170 }
 171
 172 void RegFile::changeContext(RegContextParam param, RegContextVal val)
 173 {
 174     switch(param)
 175     {
 176       case CONTEXT_CWP:
 177         intRegFile.setCWP(val);
 178         break;
 179       case CONTEXT_GLOBALS:
 180         intRegFile.setGlobals(val);
 181         break;
 182       default:
 183         panic("Tried to set illegal context parameter in the SPARC regfile.\n");
 184     }
 185 }
 186
 187 int SparcISA::InterruptLevel(uint64_t softint)
 188 {
 189     if (softint & 0x10000 || softint & 0x1)
 190         return 14;
 191
 192     int level = 14;
 193     while (level >= 0 && !(1 << (level + 1) & softint))
 194         level--;
 195     if (1 << (level + 1) & softint)
 196         return level;
 197     return 0;
 198 }
 199
 200 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 201 {
 202
 203     uint8_t tl = src->readMiscReg(MISCREG_TL);
 204
 205     // Read all the trap level dependent registers and save them off
 206     for(int i = 1; i <= MaxTL; i++)
 207     {
 208         src->setMiscReg(MISCREG_TL, i);
 209         dest->setMiscReg(MISCREG_TL, i);
 210
 211         dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
 212         dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
 213         dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
 214         dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
 215     }
 216
 217     // Save off the traplevel
 218     dest->setMiscReg(MISCREG_TL, tl);
 219     src->setMiscReg(MISCREG_TL, tl);
 220
 221
 222     // ASRs
 223     dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
 224     dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
 225     dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
 226     dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
 227     dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
 228     dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
 229     dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
 230     dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
 231     dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
 232
 233     // Priv Registers
 234     dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
 235     dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
 236     dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
 237     dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
 238     dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
 239     dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
 240     dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
 241     dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
 242     dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
 243     dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
 244     dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
 245
 246     // Hyperprivilged registers
 247     dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
 248     dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
 249     dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
 250     dest->setMiscReg(MISCREG_STRAND_STS_REG,
 251             src->readMiscReg(MISCREG_STRAND_STS_REG));
 252     dest->setMiscReg(MISCREG_HSTICK_CMPR,
 253             src->readMiscReg(MISCREG_HSTICK_CMPR));
 254
 255     // FSR
 256     dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
 257
 258     //Strand Status Register
 259     dest->setMiscReg(MISCREG_STRAND_STS_REG,
 260             src->readMiscReg(MISCREG_STRAND_STS_REG));
 261
 262     // MMU Registers
 263     dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
 264             src->readMiscReg(MISCREG_MMU_P_CONTEXT));
 265     dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
 266             src->readMiscReg(MISCREG_MMU_S_CONTEXT));
 267     dest->setMiscReg(MISCREG_MMU_PART_ID,
 268             src->readMiscReg(MISCREG_MMU_PART_ID));
 269     dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
 270             src->readMiscReg(MISCREG_MMU_LSU_CTRL));
 271
 272     dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
 273             src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
 274     dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
 275             src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
 276     dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
 277             src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
 278     dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
 279             src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
 280     dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
 281             src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
 282     dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
 283             src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
 284     dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
 285             src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
 286     dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
 287             src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
 288
 289     dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
 290             src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
 291     dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
 292             src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
 293     dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
 294             src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
 295     dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
 296             src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
 297     dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
 298             src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
 299     dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
 300             src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
 301     dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
 302             src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
 303     dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
 304             src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
 305     dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
 306             src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
 307
 308     // Scratchpad Registers
 309     dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
 310             src->readMiscReg(MISCREG_SCRATCHPAD_R0));
 311     dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
 312             src->readMiscReg(MISCREG_SCRATCHPAD_R1));
 313     dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
 314             src->readMiscReg(MISCREG_SCRATCHPAD_R2));
 315     dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
 316             src->readMiscReg(MISCREG_SCRATCHPAD_R3));
 317     dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
 318             src->readMiscReg(MISCREG_SCRATCHPAD_R4));
 319     dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
 320             src->readMiscReg(MISCREG_SCRATCHPAD_R5));
 321     dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
 322             src->readMiscReg(MISCREG_SCRATCHPAD_R6));
 323     dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
 324             src->readMiscReg(MISCREG_SCRATCHPAD_R7));
 325
 326     // Queue Registers
 327     dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
 328             src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
 329     dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
 330             src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
 331     dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
 332             src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
 333     dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
 334             src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
 335     dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
 336             src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
 337     dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
 338             src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
 339     dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
 340             src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
 341     dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
 342             src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
 343 }
 344
 345 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 346 {
 347     // First loop through the integer registers.
 348     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
 349         dest->setIntReg(i, src->readIntReg(i));
 350     }
 351
 352     // Then loop through the floating point registers.
 353     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
 354         dest->setFloatRegBits(i, src->readFloatRegBits(i));
 355     }
 356
 357     // Copy misc. registers
 358     copyMiscRegs(src, dest);
 359
 360     // Lastly copy PC/NPC
 361     dest->setPC(src->readPC());
 362     dest->setNextPC(src->readNextPC());
 363     dest->setNextNPC(src->readNextNPC());
 364 }