src/arch/sparc/regfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/regfile.hh"
  33 #include "cpu/thread_context.hh"
  34
  35 class Checkpoint;
  36
  37 using namespace SparcISA;
  38 using namespace std;
  39
  40 //RegFile class methods
  41 Addr RegFile::readPC()
  42 {
  43     return pc;
  44 }
  45
  46 void RegFile::setPC(Addr val)
  47 {
  48     pc = val;
  49 }
  50
  51 Addr RegFile::readNextPC()
  52 {
  53     return npc;
  54 }
  55
  56 void RegFile::setNextPC(Addr val)
  57 {
  58     npc = val;
  59 }
  60
  61 Addr RegFile::readNextNPC()
  62 {
  63     return nnpc;
  64 }
  65
  66 void RegFile::setNextNPC(Addr val)
  67 {
  68     nnpc = val;
  69 }
  70
  71 void RegFile::clear()
  72 {
  73     floatRegFile.clear();
  74     intRegFile.clear();
  75     miscRegFile.clear();
  76 }
  77
  78 MiscReg RegFile::readMiscRegNoEffect(int miscReg)
  79 {
  80     return miscRegFile.readRegNoEffect(miscReg);
  81 }
  82
  83 MiscReg RegFile::readMiscReg(int miscReg, ThreadContext *tc)
  84 {
  85     return miscRegFile.readReg(miscReg, tc);
  86 }
  87
  88 void RegFile::setMiscRegNoEffect(int miscReg, const MiscReg &val)
  89 {
  90     miscRegFile.setRegNoEffect(miscReg, val);
  91 }
  92
  93 void RegFile::setMiscReg(int miscReg, const MiscReg &val,
  94         ThreadContext * tc)
  95 {
  96     miscRegFile.setReg(miscReg, val, tc);
  97 }
  98
  99 FloatReg RegFile::readFloatReg(int floatReg, int width)
 100 {
 101     return floatRegFile.readReg(floatReg, width);
 102 }
 103
 104 FloatReg RegFile::readFloatReg(int floatReg)
 105 {
 106     //Use the "natural" width of a single float
 107     return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
 108 }
 109
 110 FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
 111 {
 112     return floatRegFile.readRegBits(floatReg, width);
 113 }
 114
 115 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 116 {
 117     //Use the "natural" width of a single float
 118     return floatRegFile.readRegBits(floatReg,
 119             FloatRegFile::SingleWidth);
 120 }
 121
 122 void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
 123 {
 124     floatRegFile.setReg(floatReg, val, width);
 125 }
 126
 127 void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 128 {
 129     //Use the "natural" width of a single float
 130     setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
 131 }
 132
 133 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 134 {
 135     floatRegFile.setRegBits(floatReg, val, width);
 136 }
 137
 138 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 139 {
 140     //Use the "natural" width of a single float
 141     floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 142 }
 143
 144 IntReg RegFile::readIntReg(int intReg)
 145 {
 146     return intRegFile.readReg(intReg);
 147 }
 148
 149 void RegFile::setIntReg(int intReg, const IntReg &val)
 150 {
 151     intRegFile.setReg(intReg, val);
 152 }
 153
 154 int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
 155 {
 156     int gl = tc->readMiscRegNoEffect(MISCREG_GL);
 157     int cwp = tc->readMiscRegNoEffect(MISCREG_CWP);
 158     //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
 159     int newReg;
 160     //The total number of global registers
 161     int numGlobals = (MaxGL + 1) * 8;
 162     if(reg < 8)
 163     {
 164         //Global register
 165         //Put it in the appropriate set of globals
 166         newReg = reg + gl * 8;
 167     }
 168     else if(reg < NumIntArchRegs)
 169     {
 170         //Regular windowed register
 171         //Put it in the window pointed to by cwp
 172         newReg = numGlobals +
 173             ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
 174     }
 175     else if(reg < NumIntArchRegs + NumMicroIntRegs)
 176     {
 177         //Microcode register
 178         //Displace from the end of the regular registers
 179         newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
 180     }
 181     else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
 182     {
 183         reg -= (NumIntArchRegs + NumMicroIntRegs);
 184         if(reg < 8)
 185         {
 186             //Global register from the next window
 187             //Put it in the appropriate set of globals
 188             newReg = reg + gl * 8;
 189         }
 190         else
 191         {
 192             //Windowed register from the previous window
 193             //Put it in the window before the one pointed to by cwp
 194             newReg = numGlobals +
 195                 ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
 196         }
 197     }
 198     else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
 199     {
 200         reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
 201         if(reg < 8)
 202         {
 203             //Global register from the previous window
 204             //Put it in the appropriate set of globals
 205             newReg = reg + gl * 8;
 206         }
 207         else
 208         {
 209             //Windowed register from the next window
 210             //Put it in the window after the one pointed to by cwp
 211             newReg = numGlobals +
 212                 ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
 213         }
 214     }
 215     else
 216         panic("Tried to flatten invalid register index %d!\n", reg);
 217     DPRINTF(Sparc, "Flattened register %d to %d.\n", reg, newReg);
 218     return newReg;
 219     //return intRegFile.flattenIndex(reg);
 220 }
 221
 222 void
 223 RegFile::serialize(EventManager *em, ostream &os)
 224 {
 225     intRegFile.serialize(os);
 226     floatRegFile.serialize(os);
 227     miscRegFile.serialize(em, os);
 228     SERIALIZE_SCALAR(pc);
 229     SERIALIZE_SCALAR(npc);
 230     SERIALIZE_SCALAR(nnpc);
 231 }
 232
 233 void
 234 RegFile::unserialize(EventManager *em, Checkpoint *cp, const string &section)
 235 {
 236     intRegFile.unserialize(cp, section);
 237     floatRegFile.unserialize(cp, section);
 238     miscRegFile.unserialize(em, cp, section);
 239     UNSERIALIZE_SCALAR(pc);
 240     UNSERIALIZE_SCALAR(npc);
 241     UNSERIALIZE_SCALAR(nnpc);
 242 }
 243
 244 void RegFile::changeContext(RegContextParam param, RegContextVal val)
 245 {
 246     switch(param)
 247     {
 248       case CONTEXT_CWP:
 249         intRegFile.setCWP(val);
 250         break;
 251       case CONTEXT_GLOBALS:
 252         intRegFile.setGlobals(val);
 253         break;
 254       default:
 255         panic("Tried to set illegal context parameter in the SPARC regfile.\n");
 256     }
 257 }
 258
 259 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 260 {
 261
 262     uint8_t tl = src->readMiscRegNoEffect(MISCREG_TL);
 263
 264     // Read all the trap level dependent registers and save them off
 265     for(int i = 1; i <= MaxTL; i++)
 266     {
 267         src->setMiscRegNoEffect(MISCREG_TL, i);
 268         dest->setMiscRegNoEffect(MISCREG_TL, i);
 269
 270         dest->setMiscRegNoEffect(MISCREG_TT, src->readMiscRegNoEffect(MISCREG_TT));
 271         dest->setMiscRegNoEffect(MISCREG_TPC, src->readMiscRegNoEffect(MISCREG_TPC));
 272         dest->setMiscRegNoEffect(MISCREG_TNPC, src->readMiscRegNoEffect(MISCREG_TNPC));
 273         dest->setMiscRegNoEffect(MISCREG_TSTATE, src->readMiscRegNoEffect(MISCREG_TSTATE));
 274     }
 275
 276     // Save off the traplevel
 277     dest->setMiscRegNoEffect(MISCREG_TL, tl);
 278     src->setMiscRegNoEffect(MISCREG_TL, tl);
 279
 280
 281     // ASRs
 282 //    dest->setMiscRegNoEffect(MISCREG_Y, src->readMiscRegNoEffect(MISCREG_Y));
 283 //    dest->setMiscRegNoEffect(MISCREG_CCR, src->readMiscRegNoEffect(MISCREG_CCR));
 284     dest->setMiscRegNoEffect(MISCREG_ASI, src->readMiscRegNoEffect(MISCREG_ASI));
 285     dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
 286     dest->setMiscRegNoEffect(MISCREG_FPRS, src->readMiscRegNoEffect(MISCREG_FPRS));
 287     dest->setMiscRegNoEffect(MISCREG_SOFTINT, src->readMiscRegNoEffect(MISCREG_SOFTINT));
 288     dest->setMiscRegNoEffect(MISCREG_TICK_CMPR, src->readMiscRegNoEffect(MISCREG_TICK_CMPR));
 289     dest->setMiscRegNoEffect(MISCREG_STICK, src->readMiscRegNoEffect(MISCREG_STICK));
 290     dest->setMiscRegNoEffect(MISCREG_STICK_CMPR, src->readMiscRegNoEffect(MISCREG_STICK_CMPR));
 291
 292     // Priv Registers
 293     dest->setMiscRegNoEffect(MISCREG_TICK, src->readMiscRegNoEffect(MISCREG_TICK));
 294     dest->setMiscRegNoEffect(MISCREG_TBA, src->readMiscRegNoEffect(MISCREG_TBA));
 295     dest->setMiscRegNoEffect(MISCREG_PSTATE, src->readMiscRegNoEffect(MISCREG_PSTATE));
 296     dest->setMiscRegNoEffect(MISCREG_PIL, src->readMiscRegNoEffect(MISCREG_PIL));
 297     dest->setMiscRegNoEffect(MISCREG_CWP, src->readMiscRegNoEffect(MISCREG_CWP));
 298 //    dest->setMiscRegNoEffect(MISCREG_CANSAVE, src->readMiscRegNoEffect(MISCREG_CANSAVE));
 299 //    dest->setMiscRegNoEffect(MISCREG_CANRESTORE, src->readMiscRegNoEffect(MISCREG_CANRESTORE));
 300 //    dest->setMiscRegNoEffect(MISCREG_OTHERWIN, src->readMiscRegNoEffect(MISCREG_OTHERWIN));
 301 //    dest->setMiscRegNoEffect(MISCREG_CLEANWIN, src->readMiscRegNoEffect(MISCREG_CLEANWIN));
 302 //    dest->setMiscRegNoEffect(MISCREG_WSTATE, src->readMiscRegNoEffect(MISCREG_WSTATE));
 303     dest->setMiscRegNoEffect(MISCREG_GL, src->readMiscRegNoEffect(MISCREG_GL));
 304
 305     // Hyperprivilged registers
 306     dest->setMiscRegNoEffect(MISCREG_HPSTATE, src->readMiscRegNoEffect(MISCREG_HPSTATE));
 307     dest->setMiscRegNoEffect(MISCREG_HINTP, src->readMiscRegNoEffect(MISCREG_HINTP));
 308     dest->setMiscRegNoEffect(MISCREG_HTBA, src->readMiscRegNoEffect(MISCREG_HTBA));
 309     dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
 310             src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
 311     dest->setMiscRegNoEffect(MISCREG_HSTICK_CMPR,
 312             src->readMiscRegNoEffect(MISCREG_HSTICK_CMPR));
 313
 314     // FSR
 315     dest->setMiscRegNoEffect(MISCREG_FSR, src->readMiscRegNoEffect(MISCREG_FSR));
 316
 317     //Strand Status Register
 318     dest->setMiscRegNoEffect(MISCREG_STRAND_STS_REG,
 319             src->readMiscRegNoEffect(MISCREG_STRAND_STS_REG));
 320
 321     // MMU Registers
 322     dest->setMiscRegNoEffect(MISCREG_MMU_P_CONTEXT,
 323             src->readMiscRegNoEffect(MISCREG_MMU_P_CONTEXT));
 324     dest->setMiscRegNoEffect(MISCREG_MMU_S_CONTEXT,
 325             src->readMiscRegNoEffect(MISCREG_MMU_S_CONTEXT));
 326     dest->setMiscRegNoEffect(MISCREG_MMU_PART_ID,
 327             src->readMiscRegNoEffect(MISCREG_MMU_PART_ID));
 328     dest->setMiscRegNoEffect(MISCREG_MMU_LSU_CTRL,
 329             src->readMiscRegNoEffect(MISCREG_MMU_LSU_CTRL));
 330
 331     // Scratchpad Registers
 332     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R0,
 333             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R0));
 334     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R1,
 335             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R1));
 336     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R2,
 337             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R2));
 338     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R3,
 339             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R3));
 340     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R4,
 341             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R4));
 342     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R5,
 343             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R5));
 344     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R6,
 345             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R6));
 346     dest->setMiscRegNoEffect(MISCREG_SCRATCHPAD_R7,
 347             src->readMiscRegNoEffect(MISCREG_SCRATCHPAD_R7));
 348
 349     // Queue Registers
 350     dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD,
 351             src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_HEAD));
 352     dest->setMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL,
 353             src->readMiscRegNoEffect(MISCREG_QUEUE_CPU_MONDO_TAIL));
 354     dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD,
 355             src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_HEAD));
 356     dest->setMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL,
 357             src->readMiscRegNoEffect(MISCREG_QUEUE_DEV_MONDO_TAIL));
 358     dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD,
 359             src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_HEAD));
 360     dest->setMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL,
 361             src->readMiscRegNoEffect(MISCREG_QUEUE_RES_ERROR_TAIL));
 362     dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD,
 363             src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_HEAD));
 364     dest->setMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL,
 365             src->readMiscRegNoEffect(MISCREG_QUEUE_NRES_ERROR_TAIL));
 366 }
 367
 368 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 369 {
 370     // First loop through the integer registers.
 371     for (int i = 0; i < SparcISA::NumIntRegs; ++i) {
 372         dest->setIntReg(i, src->readIntReg(i));
 373     }
 374
 375     // Then loop through the floating point registers.
 376     for (int i = 0; i < SparcISA::NumFloatRegs; ++i) {
 377         dest->setFloatRegBits(i, src->readFloatRegBits(i));
 378     }
 379
 380     // Copy misc. registers
 381     copyMiscRegs(src, dest);
 382
 383     // Lastly copy PC/NPC
 384     dest->setPC(src->readPC());
 385     dest->setNextPC(src->readNextPC());
 386     dest->setNextNPC(src->readNextNPC());
 387 }