src/arch/sparc/regfile.cc

   1 /*
   2  * Copyright (c) 2003-2005 The Regents of The University of Michigan
   3  * All rights reserved.
   4  *
   5  * Redistribution and use in source and binary forms, with or without
   6  * modification, are permitted provided that the following conditions are
   7  * met: redistributions of source code must retain the above copyright
   8  * notice, this list of conditions and the following disclaimer;
   9  * redistributions in binary form must reproduce the above copyright
  10  * notice, this list of conditions and the following disclaimer in the
  11  * documentation and/or other materials provided with the distribution;
  12  * neither the name of the copyright holders nor the names of its
  13  * contributors may be used to endorse or promote products derived from
  14  * this software without specific prior written permission.
  15  *
  16  * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
  17  * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
  18  * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
  19  * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
  20  * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
  21  * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
  22  * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
  23  * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
  24  * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
  25  * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
  26  * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
  27  *
  28  * Authors: Gabe Black
  29  *          Ali Saidi
  30  */
  31
  32 #include "arch/sparc/regfile.hh"
  33 #include "cpu/thread_context.hh"
  34
  35 class Checkpoint;
  36
  37 using namespace SparcISA;
  38 using namespace std;
  39
  40 //RegFile class methods
  41 Addr RegFile::readPC()
  42 {
  43     return pc;
  44 }
  45
  46 void RegFile::setPC(Addr val)
  47 {
  48     pc = val;
  49 }
  50
  51 Addr RegFile::readNextPC()
  52 {
  53     return npc;
  54 }
  55
  56 void RegFile::setNextPC(Addr val)
  57 {
  58     npc = val;
  59 }
  60
  61 Addr RegFile::readNextNPC()
  62 {
  63     return nnpc;
  64 }
  65
  66 void RegFile::setNextNPC(Addr val)
  67 {
  68     nnpc = val;
  69 }
  70
  71 void RegFile::clear()
  72 {
  73     floatRegFile.clear();
  74     intRegFile.clear();
  75     miscRegFile.clear();
  76 }
  77
  78 MiscReg RegFile::readMiscReg(int miscReg)
  79 {
  80     return miscRegFile.readReg(miscReg);
  81 }
  82
  83 MiscReg RegFile::readMiscRegWithEffect(int miscReg, ThreadContext *tc)
  84 {
  85     return miscRegFile.readRegWithEffect(miscReg, tc);
  86 }
  87
  88 void RegFile::setMiscReg(int miscReg, const MiscReg &val)
  89 {
  90     miscRegFile.setReg(miscReg, val);
  91 }
  92
  93 void RegFile::setMiscRegWithEffect(int miscReg, const MiscReg &val,
  94         ThreadContext * tc)
  95 {
  96     miscRegFile.setRegWithEffect(miscReg, val, tc);
  97 }
  98
  99 FloatReg RegFile::readFloatReg(int floatReg, int width)
 100 {
 101     return floatRegFile.readReg(floatReg, width);
 102 }
 103
 104 FloatReg RegFile::readFloatReg(int floatReg)
 105 {
 106     //Use the "natural" width of a single float
 107     return floatRegFile.readReg(floatReg, FloatRegFile::SingleWidth);
 108 }
 109
 110 FloatRegBits RegFile::readFloatRegBits(int floatReg, int width)
 111 {
 112     return floatRegFile.readRegBits(floatReg, width);
 113 }
 114
 115 FloatRegBits RegFile::readFloatRegBits(int floatReg)
 116 {
 117     //Use the "natural" width of a single float
 118     return floatRegFile.readRegBits(floatReg,
 119             FloatRegFile::SingleWidth);
 120 }
 121
 122 void RegFile::setFloatReg(int floatReg, const FloatReg &val, int width)
 123 {
 124     floatRegFile.setReg(floatReg, val, width);
 125 }
 126
 127 void RegFile::setFloatReg(int floatReg, const FloatReg &val)
 128 {
 129     //Use the "natural" width of a single float
 130     setFloatReg(floatReg, val, FloatRegFile::SingleWidth);
 131 }
 132
 133 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val, int width)
 134 {
 135     floatRegFile.setRegBits(floatReg, val, width);
 136 }
 137
 138 void RegFile::setFloatRegBits(int floatReg, const FloatRegBits &val)
 139 {
 140     //Use the "natural" width of a single float
 141     floatRegFile.setRegBits(floatReg, val, FloatRegFile::SingleWidth);
 142 }
 143
 144 IntReg RegFile::readIntReg(int intReg)
 145 {
 146     return intRegFile.readReg(intReg);
 147 }
 148
 149 void RegFile::setIntReg(int intReg, const IntReg &val)
 150 {
 151     intRegFile.setReg(intReg, val);
 152 }
 153
 154 int SparcISA::flattenIntIndex(ThreadContext * tc, int reg)
 155 {
 156     int gl = tc->readMiscReg(MISCREG_GL);
 157     int cwp = tc->readMiscReg(MISCREG_CWP);
 158     //DPRINTF(Sparc, "Global Level = %d, Current Window Pointer = %d\n", gl, cwp);
 159     int newReg;
 160     //The total number of global registers
 161     int numGlobals = (MaxGL + 1) * 8;
 162     if(reg < 8)
 163     {
 164         //Global register
 165         //Put it in the appropriate set of globals
 166         newReg = reg + gl * 8;
 167     }
 168     else if(reg < NumIntArchRegs)
 169     {
 170         //Regular windowed register
 171         //Put it in the window pointed to by cwp
 172         newReg = numGlobals +
 173             ((reg - 8 - cwp * 16 + NWindows * 16) % (NWindows * 16));
 174     }
 175     else if(reg < NumIntArchRegs + NumMicroIntRegs)
 176     {
 177         //Microcode register
 178         //Displace from the end of the regular registers
 179         newReg = reg - NumIntArchRegs + numGlobals + NWindows * 16;
 180     }
 181     else if(reg < 2 * NumIntArchRegs + NumMicroIntRegs)
 182     {
 183         reg -= (NumIntArchRegs + NumMicroIntRegs);
 184         if(reg < 8)
 185         {
 186             //Global register from the next window
 187             //Put it in the appropriate set of globals
 188             newReg = reg + gl * 8;
 189         }
 190         else
 191         {
 192             //Windowed register from the previous window
 193             //Put it in the window before the one pointed to by cwp
 194             newReg = numGlobals +
 195                 ((reg - 8 - (cwp - 1) * 16 + NWindows * 16) % (NWindows * 16));
 196         }
 197     }
 198     else if(reg < 3 * NumIntArchRegs + NumMicroIntRegs)
 199     {
 200         reg -= (2 * NumIntArchRegs + NumMicroIntRegs);
 201         if(reg < 8)
 202         {
 203             //Global register from the previous window
 204             //Put it in the appropriate set of globals
 205             newReg = reg + gl * 8;
 206         }
 207         else
 208         {
 209             //Windowed register from the next window
 210             //Put it in the window after the one pointed to by cwp
 211             newReg = numGlobals +
 212                 ((reg - 8 - (cwp + 1) * 16 + NWindows * 16) % (NWindows * 16));
 213         }
 214     }
 215     else
 216         panic("Tried to flatten invalid register index %d!\n", reg);
 217     DPRINTF(Sparc, "Flattened register %d to %d.\n", reg, newReg);
 218     return newReg;
 219     //return intRegFile.flattenIndex(reg);
 220 }
 221
 222 void RegFile::serialize(std::ostream &os)
 223 {
 224     intRegFile.serialize(os);
 225     floatRegFile.serialize(os);
 226     miscRegFile.serialize(os);
 227     SERIALIZE_SCALAR(pc);
 228     SERIALIZE_SCALAR(npc);
 229     SERIALIZE_SCALAR(nnpc);
 230 }
 231
 232 void RegFile::unserialize(Checkpoint *cp, const std::string &section)
 233 {
 234     intRegFile.unserialize(cp, section);
 235     floatRegFile.unserialize(cp, section);
 236     miscRegFile.unserialize(cp, section);
 237     UNSERIALIZE_SCALAR(pc);
 238     UNSERIALIZE_SCALAR(npc);
 239     UNSERIALIZE_SCALAR(nnpc);
 240 }
 241
 242 void RegFile::changeContext(RegContextParam param, RegContextVal val)
 243 {
 244     switch(param)
 245     {
 246       case CONTEXT_CWP:
 247         intRegFile.setCWP(val);
 248         break;
 249       case CONTEXT_GLOBALS:
 250         intRegFile.setGlobals(val);
 251         break;
 252       default:
 253         panic("Tried to set illegal context parameter in the SPARC regfile.\n");
 254     }
 255 }
 256
 257 void SparcISA::copyMiscRegs(ThreadContext *src, ThreadContext *dest)
 258 {
 259
 260     uint8_t tl = src->readMiscReg(MISCREG_TL);
 261
 262     // Read all the trap level dependent registers and save them off
 263     for(int i = 1; i <= MaxTL; i++)
 264     {
 265         src->setMiscReg(MISCREG_TL, i);
 266         dest->setMiscReg(MISCREG_TL, i);
 267
 268         dest->setMiscReg(MISCREG_TT, src->readMiscReg(MISCREG_TT));
 269         dest->setMiscReg(MISCREG_TPC, src->readMiscReg(MISCREG_TPC));
 270         dest->setMiscReg(MISCREG_TNPC, src->readMiscReg(MISCREG_TNPC));
 271         dest->setMiscReg(MISCREG_TSTATE, src->readMiscReg(MISCREG_TSTATE));
 272     }
 273
 274     // Save off the traplevel
 275     dest->setMiscReg(MISCREG_TL, tl);
 276     src->setMiscReg(MISCREG_TL, tl);
 277
 278
 279     // ASRs
 280 //    dest->setMiscReg(MISCREG_Y, src->readMiscReg(MISCREG_Y));
 281 //    dest->setMiscReg(MISCREG_CCR, src->readMiscReg(MISCREG_CCR));
 282     dest->setMiscReg(MISCREG_ASI, src->readMiscReg(MISCREG_ASI));
 283     dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
 284     dest->setMiscReg(MISCREG_FPRS, src->readMiscReg(MISCREG_FPRS));
 285     dest->setMiscReg(MISCREG_SOFTINT, src->readMiscReg(MISCREG_SOFTINT));
 286     dest->setMiscReg(MISCREG_TICK_CMPR, src->readMiscReg(MISCREG_TICK_CMPR));
 287     dest->setMiscReg(MISCREG_STICK, src->readMiscReg(MISCREG_STICK));
 288     dest->setMiscReg(MISCREG_STICK_CMPR, src->readMiscReg(MISCREG_STICK_CMPR));
 289
 290     // Priv Registers
 291     dest->setMiscReg(MISCREG_TICK, src->readMiscReg(MISCREG_TICK));
 292     dest->setMiscReg(MISCREG_TBA, src->readMiscReg(MISCREG_TBA));
 293     dest->setMiscReg(MISCREG_PSTATE, src->readMiscReg(MISCREG_PSTATE));
 294     dest->setMiscReg(MISCREG_PIL, src->readMiscReg(MISCREG_PIL));
 295     dest->setMiscReg(MISCREG_CWP, src->readMiscReg(MISCREG_CWP));
 296 //    dest->setMiscReg(MISCREG_CANSAVE, src->readMiscReg(MISCREG_CANSAVE));
 297 //    dest->setMiscReg(MISCREG_CANRESTORE, src->readMiscReg(MISCREG_CANRESTORE));
 298 //    dest->setMiscReg(MISCREG_OTHERWIN, src->readMiscReg(MISCREG_OTHERWIN));
 299 //    dest->setMiscReg(MISCREG_CLEANWIN, src->readMiscReg(MISCREG_CLEANWIN));
 300 //    dest->setMiscReg(MISCREG_WSTATE, src->readMiscReg(MISCREG_WSTATE));
 301     dest->setMiscReg(MISCREG_GL, src->readMiscReg(MISCREG_GL));
 302
 303     // Hyperprivilged registers
 304     dest->setMiscReg(MISCREG_HPSTATE, src->readMiscReg(MISCREG_HPSTATE));
 305     dest->setMiscReg(MISCREG_HINTP, src->readMiscReg(MISCREG_HINTP));
 306     dest->setMiscReg(MISCREG_HTBA, src->readMiscReg(MISCREG_HTBA));
 307     dest->setMiscReg(MISCREG_STRAND_STS_REG,
 308             src->readMiscReg(MISCREG_STRAND_STS_REG));
 309     dest->setMiscReg(MISCREG_HSTICK_CMPR,
 310             src->readMiscReg(MISCREG_HSTICK_CMPR));
 311
 312     // FSR
 313     dest->setMiscReg(MISCREG_FSR, src->readMiscReg(MISCREG_FSR));
 314
 315     //Strand Status Register
 316     dest->setMiscReg(MISCREG_STRAND_STS_REG,
 317             src->readMiscReg(MISCREG_STRAND_STS_REG));
 318
 319     // MMU Registers
 320     dest->setMiscReg(MISCREG_MMU_P_CONTEXT,
 321             src->readMiscReg(MISCREG_MMU_P_CONTEXT));
 322     dest->setMiscReg(MISCREG_MMU_S_CONTEXT,
 323             src->readMiscReg(MISCREG_MMU_S_CONTEXT));
 324     dest->setMiscReg(MISCREG_MMU_PART_ID,
 325             src->readMiscReg(MISCREG_MMU_PART_ID));
 326     dest->setMiscReg(MISCREG_MMU_LSU_CTRL,
 327             src->readMiscReg(MISCREG_MMU_LSU_CTRL));
 328
 329     dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0,
 330             src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS0));
 331     dest->setMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1,
 332             src->readMiscReg(MISCREG_MMU_ITLB_C0_TSB_PS1));
 333     dest->setMiscReg(MISCREG_MMU_ITLB_C0_CONFIG,
 334             src->readMiscReg(MISCREG_MMU_ITLB_C0_CONFIG));
 335     dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0,
 336             src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS0));
 337     dest->setMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1,
 338             src->readMiscReg(MISCREG_MMU_ITLB_CX_TSB_PS1));
 339     dest->setMiscReg(MISCREG_MMU_ITLB_CX_CONFIG,
 340             src->readMiscReg(MISCREG_MMU_ITLB_CX_CONFIG));
 341     dest->setMiscReg(MISCREG_MMU_ITLB_SFSR,
 342             src->readMiscReg(MISCREG_MMU_ITLB_SFSR));
 343     dest->setMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS,
 344             src->readMiscReg(MISCREG_MMU_ITLB_TAG_ACCESS));
 345
 346     dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0,
 347             src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS0));
 348     dest->setMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1,
 349             src->readMiscReg(MISCREG_MMU_DTLB_C0_TSB_PS1));
 350     dest->setMiscReg(MISCREG_MMU_DTLB_C0_CONFIG,
 351             src->readMiscReg(MISCREG_MMU_DTLB_C0_CONFIG));
 352     dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0,
 353             src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS0));
 354     dest->setMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1,
 355             src->readMiscReg(MISCREG_MMU_DTLB_CX_TSB_PS1));
 356     dest->setMiscReg(MISCREG_MMU_DTLB_CX_CONFIG,
 357             src->readMiscReg(MISCREG_MMU_DTLB_CX_CONFIG));
 358     dest->setMiscReg(MISCREG_MMU_DTLB_SFSR,
 359             src->readMiscReg(MISCREG_MMU_DTLB_SFSR));
 360     dest->setMiscReg(MISCREG_MMU_DTLB_SFAR,
 361             src->readMiscReg(MISCREG_MMU_DTLB_SFAR));
 362     dest->setMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS,
 363             src->readMiscReg(MISCREG_MMU_DTLB_TAG_ACCESS));
 364
 365     // Scratchpad Registers
 366     dest->setMiscReg(MISCREG_SCRATCHPAD_R0,
 367             src->readMiscReg(MISCREG_SCRATCHPAD_R0));
 368     dest->setMiscReg(MISCREG_SCRATCHPAD_R1,
 369             src->readMiscReg(MISCREG_SCRATCHPAD_R1));
 370     dest->setMiscReg(MISCREG_SCRATCHPAD_R2,
 371             src->readMiscReg(MISCREG_SCRATCHPAD_R2));
 372     dest->setMiscReg(MISCREG_SCRATCHPAD_R3,
 373             src->readMiscReg(MISCREG_SCRATCHPAD_R3));
 374     dest->setMiscReg(MISCREG_SCRATCHPAD_R4,
 375             src->readMiscReg(MISCREG_SCRATCHPAD_R4));
 376     dest->setMiscReg(MISCREG_SCRATCHPAD_R5,
 377             src->readMiscReg(MISCREG_SCRATCHPAD_R5));
 378     dest->setMiscReg(MISCREG_SCRATCHPAD_R6,
 379             src->readMiscReg(MISCREG_SCRATCHPAD_R6));
 380     dest->setMiscReg(MISCREG_SCRATCHPAD_R7,
 381             src->readMiscReg(MISCREG_SCRATCHPAD_R7));
 382
 383     // Queue Registers
 384     dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD,
 385             src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_HEAD));
 386     dest->setMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL,
 387             src->readMiscReg(MISCREG_QUEUE_CPU_MONDO_TAIL));
 388     dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD,
 389             src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_HEAD));
 390     dest->setMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL,
 391             src->readMiscReg(MISCREG_QUEUE_DEV_MONDO_TAIL));
 392     dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD,
 393             src->readMiscReg(MISCREG_QUEUE_RES_ERROR_HEAD));
 394     dest->setMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL,
 395             src->readMiscReg(MISCREG_QUEUE_RES_ERROR_TAIL));
 396     dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD,
 397             src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_HEAD));
 398     dest->setMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL,
 399             src->readMiscReg(MISCREG_QUEUE_NRES_ERROR_TAIL));
 400 }
 401
 402 void SparcISA::copyRegs(ThreadContext *src, ThreadContext *dest)
 403 {
 404     // First loop through the integer registers.
 405     for (int i = 0; i < TheISA::NumIntRegs; ++i) {
 406         dest->setIntReg(i, src->readIntReg(i));
 407     }
 408
 409     // Then loop through the floating point registers.
 410     for (int i = 0; i < TheISA::NumFloatRegs; ++i) {
 411         dest->setFloatRegBits(i, src->readFloatRegBits(i));
 412     }
 413
 414     // Copy misc. registers
 415     copyMiscRegs(src, dest);
 416
 417     // Lastly copy PC/NPC
 418     dest->setPC(src->readPC());
 419     dest->setNextPC(src->readNextPC());
 420     dest->setNextNPC(src->readNextNPC());
 421 }