Only issue responses if we aren;t already blocked
[gem5.git] / src / arch / sparc / regfile.hh
1 /*
2 * Copyright (c) 2003-2005 The Regents of The University of Michigan
3 * All rights reserved.
4 *
5 * Redistribution and use in source and binary forms, with or without
6 * modification, are permitted provided that the following conditions are
7 * met: redistributions of source code must retain the above copyright
8 * notice, this list of conditions and the following disclaimer;
9 * redistributions in binary form must reproduce the above copyright
10 * notice, this list of conditions and the following disclaimer in the
11 * documentation and/or other materials provided with the distribution;
12 * neither the name of the copyright holders nor the names of its
13 * contributors may be used to endorse or promote products derived from
14 * this software without specific prior written permission.
15 *
16 * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
17 * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
18 * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
19 * A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
20 * OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
21 * SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
22 * LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
23 * DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
24 * THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
25 * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
26 * OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
27 *
28 * Authors: Gabe Black
29 * Ali Saidi
30 */
31
32 #ifndef __ARCH_SPARC_REGFILE_HH__
33 #define __ARCH_SPARC_REGFILE_HH__
34
35 #include "arch/sparc/faults.hh"
36 #include "arch/sparc/floatregfile.hh"
37 #include "arch/sparc/intregfile.hh"
38 #include "arch/sparc/isa_traits.hh"
39 #include "arch/sparc/miscregfile.hh"
40 #include "arch/sparc/types.hh"
41 #include "sim/host.hh"
42
43 #include <string>
44
45 class Checkpoint;
46
47 namespace SparcISA
48 {
49 class RegFile
50 {
51 protected:
52 Addr pc; // Program Counter
53 Addr npc; // Next Program Counter
54 Addr nnpc;
55
56 public:
57 Addr readPC();
58 void setPC(Addr val);
59
60 Addr readNextPC();
61 void setNextPC(Addr val);
62
63 Addr readNextNPC();
64 void setNextNPC(Addr val);
65
66 protected:
67 IntRegFile intRegFile; // integer register file
68 FloatRegFile floatRegFile; // floating point register file
69 MiscRegFile miscRegFile; // control register file
70
71 public:
72
73 void clear();
74
75 int FlattenIntIndex(int reg);
76
77 MiscReg readMiscReg(int miscReg);
78
79 MiscReg readMiscRegWithEffect(int miscReg,
80 Fault &fault, ThreadContext *tc);
81
82 Fault setMiscReg(int miscReg, const MiscReg &val);
83
84 Fault setMiscRegWithEffect(int miscReg, const MiscReg &val,
85 ThreadContext * tc);
86
87 FloatReg readFloatReg(int floatReg, int width);
88
89 FloatReg readFloatReg(int floatReg);
90
91 FloatRegBits readFloatRegBits(int floatReg, int width);
92
93 FloatRegBits readFloatRegBits(int floatReg);
94
95 Fault setFloatReg(int floatReg, const FloatReg &val, int width);
96
97 Fault setFloatReg(int floatReg, const FloatReg &val);
98
99 Fault setFloatRegBits(int floatReg, const FloatRegBits &val, int width);
100
101 Fault setFloatRegBits(int floatReg, const FloatRegBits &val);
102
103 IntReg readIntReg(int intReg);
104
105 Fault setIntReg(int intReg, const IntReg &val);
106
107 void serialize(std::ostream &os);
108 void unserialize(Checkpoint *cp, const std::string &section);
109
110 public:
111
112 void changeContext(RegContextParam param, RegContextVal val);
113 };
114
115 void copyRegs(ThreadContext *src, ThreadContext *dest);
116
117 void copyMiscRegs(ThreadContext *src, ThreadContext *dest);
118
119 int InterruptLevel(uint64_t softint);
120
121 } // namespace SparcISA
122
123 #endif